DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 5/8/2026 in which claims 1 and 6 were amended.
Claims 1-20 are pending with claims 1-10 presented for examination and claims 11-20 remaining withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohki (US 2012/0217544 and Ohki hereinafter).
As to claims 1-4: Ohki discloses [claim 1] an integrated circuit structure (Fig. 7D; [0108]-[0109]), comprising: a layer (2; [0109]) comprising gallium and nitrogen (GaN; [0109]), the layer (2) comprising gallium and nitrogen (GaN) above a silicon substrate (1 can be SiC, which is a silicon substrate as it comprises silicon; [0109]); a gate structure (comprising 7 and 9; [0110]) over the layer (2) comprising gallium and nitrogen (GaN), the gate structure (comprising 7 and 9) comprising a gate electrode (7; [0110]) on a gate dielectric layer (9; [0110]); a source region (5; [0109]) on a first side (left side) of the gate structure (comprising 7 and 9); a drain region (6; [0109]) on a second side (right side) of the gate structure (comprising 7 and 9); and a source field plate (8 can be connected to source and is interpreted to be a source field plate; [0110] and [0035]) laterally between the gate structure (comprising 7 and 9) and the drain region (6), the source field plate (8) laterally separated from the gate structure (8 is laterally separated from the gate electrode 7), and the source field plate (8) on the gate dielectric layer (9), wherein the gate dielectric layer (9) is continuous between the gate electrode (7) and the source field plate (8); [claim 2] wherein a voltage associated with the source field plate (8) is different from a gate voltage associated with the gate structure (the source field plate 8 is connected to the source electrode, which is different from the voltage of the gate electrode 7 that is connected to the gate terminal as they are two different sources of voltage; [0035]); [claim 3] wherein the source field plate (8) has a top surface (topmost surface), wherein the top surface (topmost surface) of the source field plate (8) is substantially coplanar (the gate electrode 7 and the source field plate 8 can be formed at the same time to have an identical structure and will thus have coplanar top surfaces; [0110]) with a top surface (topmost surface) of the gate structure (7); [claim 4] wherein the gate structure (7) has a T-shaped gate structure (Fig. 8D; the shape of the gate electrode 7 is T-shaped and this shape can be applied to the embodiment of Fig. 7D; [0124] and [0139]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ohki in view of Then et al (US 2020/0098885 and Then hereinafter).
Although the structure disclosed by Ohki shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
further comprising: a layer comprising aluminum and nitrogen, the layer comprising aluminum and nitrogen between the layer comprising gallium and nitrogen and the silicon substrate.
Ohki discloses a semiconductor substrate structure comprising a SiC substrate and a GaN layer thereon.
Then discloses that when forming a GaN on a SiC substrate, an AlN buffer layer can be used between them, see [0017] and [0027].
Given the teachings of Then, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Ohki by employing the well-known or conventional features of III-V device fabrication, such as displayed by Then, by employing an AlN buffer layer between a SiC substrate and an overlying GaN layer in order to improve growth conditions and/or prevent the GaN layer from reacting with the SiC substrate ([0027]).
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sihu et al (CN 113241378 and Sihu hereinafter; a machine translation is used as an English language equivalent) in view of Ohki.
As to claims 6-10: Sihu discloses [claim 6] a computing device (Fig. 8; 1000; [0151]), comprising: a board (1002; [0151]); and a component (integrated circuit structure formed within 1006; [0155]) coupled to the board (1002), the component including an integrated circuit structure (integrated circuit structure; [0155]); [claim 7] further comprising: a memory (DRAM; [0152]) coupled to the board (1002); [claim 8] further comprising: a power delivery chip (power amplifier will deliver amplified power to components; [0152]) coupled to the board (1002); [claim 9] further comprising: a camera (camera; [0152]) coupled to the board (1002); [claim 10] wherein the component (integrated circuit structure) is a packaged integrated circuit die ([0155]).
Sihu fails to expressly disclose where the integrated circuit structure comprises [claim 6] a layer comprising gallium and nitrogen, the layer comprising gallium and nitrogen above a silicon substrate; a gate structure over the layer comprising gallium and nitrogen, the gate structure comprising a gate electrode on a gate dielectric layer; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a source field plate laterally between the gate structure and the drain region, the source field plate laterally separated from the gate structure, and the source field plate on the gate dielectric layer, wherein the gate dielectric layer is continuous between the gate electrode and the source field plate.
Sihu discloses that the integrated circuit structure can comprise a HEMT ([0105]).
Ohki discloses a HEMT comprising [claim 6] a layer (Fig. 7D; 2; [0109]) comprising gallium and nitrogen (GaN; [0109]), the layer (2) comprising gallium and nitrogen (GaN) above a silicon substrate (1 can be SiC, which is a silicon substrate as it comprises silicon; [0109]); a gate structure (comprising 7 and 9; [0110]) over the layer (2) comprising gallium and nitrogen (GaN), the gate structure (comprising 7 and 9) comprising a gate electrode (7; [0110]) on a gate dielectric layer (9; [0110]); a source region (5; [0109]) on a first side (left side) of the gate structure (comprising 7 and 9); a drain region (6; [0109]) on a second side (right side) of the gate structure (comprising 7 and 9); and a source field plate (8 can be connected to source and is interpreted to be a source field plate; [0110] and [0035]) laterally between the gate structure (comprising 7 and 9) and the drain region (6), the source field plate (8) laterally separated from the gate structure (8 is laterally separated from the gate electrode 7), and the source field plate (8) on the gate dielectric layer (9), wherein the gate dielectric layer (9) is continuous between the gate electrode (7) and the source field plate (8).
Given the teachings of Ohki, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Sihu by employing the well-known or conventional features of HEMT fabrication, such as displayed by Ohki, by employing a GaN-based HEMT structure with a source field plate laterally separated from the gate structure and both are on a gate dielectric in order to provide a HEMT with improved withstanding voltage while suppressing any increase in the on-resistance ([0026]).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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