DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 8-12, filed 04/21/2026, with respect to the rejection(s) of claims 1, 3-6, and 8-20 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Young et al. (US 20210408049 A1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 4 are rejected under 35 U.S.C. 102(a)(1)(a)(2) as being anticipated by Young et al. (US 20210408049 A1).
Regarding claim 1, Young discloses an integrated circuit structure, comprising:
a front side structure (annotated below) comprising:
a device layer (130) having a plurality of fin-based select transistors (TR); ([0009], Fig. 10)
a plurality of metallization layers (134/136) above the plurality of fin-based select transistors (TR); (0054]-[0056], Fig. 11 and 12) and
a plurality of vias below (136a) and coupled to the plurality of fin-based select transistors (TR); ([0055], Fig. 11) and
a backside structure (annotated below) below the plurality of vias (136a) of the device layer (130), the backside structure including a memory layer (144) coupled to the plurality of fin-based select transistors (TR) by the plurality of vias (136a), wherein the memory layer comprises a plurality of capacitor structures (142), the plurality of capacitor structures comprising a first layer of capacitor structures (annotated below) vertically over a second layer of capacitor structures (annotated below). (Fig. 18)
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Regarding claim 3, Young discloses the integrated circuit structure of claim 1, wherein the plurality of capacitor structures (142) is a ferroelectric capacitor array. ([0057], Fig. 13)
Regarding claim 4, Young discloses the integrated circuit structure of claim 1, wherein the memory layer (144) comprises a plurality of magnetic random access memory devices. ([0057], Fig. 13)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Young et al. (US 20210408049 A1).
Regarding claim 6, Young discloses an integrated circuit structure, comprising:
a front side structure (annotated below) comprising:
a device layer (130) having a plurality of transistors (TR); ([0009], Fig. 10)
a plurality of metallization layers (134/136) above the plurality of transistors (TR); (0054]-[0056], Fig. 11 and 12) and
a plurality of vias below (136a) and coupled to the plurality of transistors (TR); ([0055], Fig. 11) and
a backside structure (annotated below) below the plurality of vias (136a) of the device layer (130), the backside structure including a memory layer (144) coupled to the plurality of transistors (TR) by the plurality of vias (136a), wherein the memory layer comprises a plurality of capacitor structures (142), the plurality of capacitor structures comprising a first layer of capacitor structures (annotated below) vertically over a second layer of capacitor structures (annotated below). (Fig. 18)
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Young does not explicitly disclose:
Nanowire-based select transistors
However, It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Young to use a nanowire-based select transistor as an intended purpose has been recognized to be motivation to combine. MPEP 2144.07 in order to have “reductions in minimum feature size, which allows more components to be integrated into a given area” (Young, [0002])
Regarding claim 8, Young discloses the integrated circuit structure of claim 6, wherein the plurality of capacitor structures (142) is a ferroelectric capacitor array. ([0057], Fig. 13)
Regarding claim 9, Young discloses the integrated circuit structure of claim 6, wherein the memory layer (144) comprises a plurality of magnetic random access memory devices. ([0057], Fig. 13)
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Young et al. (US 20210408049 A1) as applied to claims 1 and 6 above, and further in view of Sharma et al. (US 20200411078 A1).
Regarding claim 5, Young discloses the integrated circuit structure of claim 1. Young does not disclose wherein the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor).
However, Sharma discloses:
the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) (130). ([0023], [0050]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Young and Sharma for the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) in order to “enable a memory density improvement by including multiple layers of memory cell arrays.” (Sharma, [0021])
Regarding claim 10, Young discloses the integrated circuit structure of claim 6. Young does not disclose wherein the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor).
However, Sharma discloses:
the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) (130). ([0023], [0050]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Young and Sharma for the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) in order to “enable a memory density improvement by including multiple layers of memory cell arrays.” (Sharma, [0021])
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US 20210398993 A1) in view of Young et al. (US 20210408049 A1).
Regarding claim 11, Haratipour discloses a computing device (2400), comprising:
a board ([0113], Fig. 12); and
a component ([0113]) coupled to the board ([0113]), the component ([0113]) including an integrated circuit structure (2100),
and a plurality of fin-based select transistors (110), ([0032], Fig. 4)
Haratipour does not disclose:
a front side structure comprising: a device layer having a plurality of fin-based select transistors;
a plurality of metallization layers above the plurality of fin-based select transistors; and
a plurality of vias below and coupled to the plurality of fin-based select transistors; and
a backside structure below the plurality of vias of the device layer, the backside structure including a memory layer coupled to the plurality of fin-based select transistors by the plurality of vias.
However, Young discloses:
a front side structure (annotated below) comprising:
a device layer (130) having a plurality of fin-based select transistors (TR); ([0009], Fig. 10)
a plurality of metallization layers (134/136) above the plurality of fin-based select transistors (TR); (0054]-[0056], Fig. 11 and 12) and
a plurality of vias below (136a) and coupled to the plurality of fin-based select transistors (TR); ([0055], Fig. 11) and
a backside structure (annotated below) below the plurality of vias (136a) of the device layer (130), the backside structure including a memory layer (144) coupled to the plurality of fin-based select transistors (TR) by the plurality of vias (136a), wherein the memory layer comprises a plurality of capacitor structures (142), the plurality of capacitor structures comprising a first layer of capacitor structures (annotated below) vertically over a second layer of capacitor structures (annotated below). (Fig. 18)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Young and Yamazaki to arrive at the claimed invention in order to “form the memory cell array having high capacity and/or high density.” (Young, [0073])
Regarding claim 12, Haratipour discloses the computing device of claim 11, further comprising: a memory (2404) coupled to the board ([0113]). ([0115], Fig. 12)
Regarding claim 13, Haratipour discloses the computing device of claim 11, further comprising: a communication chip (2412) coupled to the board ([0113]). ([0116], Fig. 12)
Regarding claim 14, Haratipour discloses the computing device of claim 11, wherein the component ([0113]) is a packaged integrated circuit die (2100). ([0112], Fig. 12)
Regarding claim 15, Haratipour discloses the computing device of claim 11, wherein the component ([0113]) is selected from the group consisting of a processor, a communications chip, and a digital signal processor. ([0112]- [0115], Fig. 12)
Regarding claim 16, Haratipour discloses a computing device (2400), comprising:
a board ([0113], Fig. 12); and
a component ([0113]) coupled to the board ([0113]), the component ([0113]) including an integrated circuit structure (2100),
and a plurality of nanowire-based select transistors (110), ([0032], Fig. 4)
Haratipour does not disclose:
a front side structure comprising: a device layer having a plurality of nanowire-based select transistors;
a plurality of metallization layers above the plurality of nanowire-based select transistors; and
a plurality of vias below and coupled to the plurality of nanowire-based select transistors; and
a backside structure below the plurality of vias of the device layer, the backside structure including a memory layer coupled to the plurality of nanowire-based select transistors by the plurality of vias.
However, Young discloses:
a front side structure (annotated below) comprising:
a device layer (130) having a plurality of transistors (TR); ([0009], Fig. 10)
a plurality of metallization layers (134/136) above the plurality of transistors (TR); (0054]-[0056], Fig. 11 and 12) and
a plurality of vias below (136a) and coupled to the plurality of transistors (TR); ([0055], Fig. 11) and
a backside structure (annotated below) below the plurality of vias (136a) of the device layer (130), the backside structure including a memory layer (144) coupled to the plurality of transistors (TR) by the plurality of vias (136a), wherein the memory layer comprises a plurality of capacitor structures (142), the plurality of capacitor structures comprising a first layer of capacitor structures (annotated below) vertically over a second layer of capacitor structures (annotated below). (Fig. 18)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Young and Yamazaki to arrive at the claimed invention in order to “form the memory cell array having high capacity and/or high density.” (Young, [0073])
Young does not explicitly disclose:
Nanowire-based select transistors
However, It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Young to use a nanowire-based select transistor as an intended purpose has been recognized to be motivation to combine. MPEP 2144.07 in order to have “reductions in minimum feature size, which allows more components to be integrated into a given area” (Young, [0002])
Regarding claim 17, Haratipour discloses the computing device of claim 16, further comprising: a memory (2404) coupled to the board ([0113]). ([0115], Fig. 12)
Regarding claim 18, Haratipour discloses the computing device of claim 16, further comprising: a communication chip (2412) coupled to the board ([0113]). ([0116], Fig. 12)
Regarding claim 19, Haratipour discloses the computing device of claim 16, wherein the component ([0113]) is a packaged integrated circuit die (2100). ([0112], Fig. 12)
Regarding claim 20, Haratipour discloses the computing device of claim 16, wherein the component ([0113]) is selected from the group consisting of a processor, a communications chip, and a digital signal processor. ([0112]- [0115], Fig. 12)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gomes et al. (US 20220375916 A1) discloses an IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM) but does not disclose all the features as required by the claim.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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