DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/04/2024 is being considered by the examiner.
Drawings
The drawings submitted on 12/24/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20170033109 A1) in view of Haratipour et al. (US 20210398993 A1).
Regarding claim 1, Yamazaki discloses an integrated circuit structure, comprising:
a front side structure (annotated below) comprising:
a device layer (L6) having a transistor (OS2); ([0074], Fig. 1)
a plurality of metallization layers (in L7) above the transistor (OS2); ([0075], Fig. 1) and
a plurality of vias (44 and 24) below and coupled to the transistor (OS2); ([0186]) and
a backside structure (annotated below) below the plurality of vias (44 and 24) of the device layer (L6), the backside structure (L4-L5) including a memory layer (L5) coupled to the transistor (OS2) by the plurality of vias (44 and 24). (Fig. 1 and 5A)
PNG
media_image1.png
769
683
media_image1.png
Greyscale
Yamazaki does not disclose:
a plurality of fin-based select transistors
However, Haratipour discloses:
a plurality of fin-based select transistors (110), ([0032], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki and Haratipour to have a plurality of fin-based select transistors because they are “promising alternatives to transistors with planar architecture.” (Haratipour, [0032])
Regarding claim 2, Yamazaki discloses the integrated circuit structure of claim 1, wherein the memory layer (L5) comprises a plurality of capacitor structures (C0). ([0060], Fig. 1)
Regarding claim 3, Yamazaki discloses the integrated circuit structure of claim 2. Yamazaki does not disclose wherein the plurality of capacitor structures is a ferroelectric capacitor array.
However, Haratipour discloses:
the plurality of capacitor structures (120) is a ferroelectric capacitor array ([0051], Fig. 4).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki and Haratipour for the plurality of capacitor structures is a ferroelectric capacitor array because “FE memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, FE memories have the potential to be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology.” (Haratipour, [0016])
Regarding claim 4, Yamazaki discloses the integrated circuit structure of claim 1. Yamazaki does not disclose wherein the memory layer comprises a plurality of magnetic random access memory devices.
However, Haratipour discloses:
the memory layer (labeled 220 in Fig. 2) comprises a plurality of magnetic random access memory devices. ([0115], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki and Haratipour for the memory layer comprises a plurality of magnetic random access memory devices because it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987). See MPEP 2144. Furthermore, “FE memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, FE memories have the potential to be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology.” (Haratipour, [0016])
Regarding claim 6, Yamazaki discloses an integrated circuit structure, comprising:
a front side structure (annotated below) comprising:
a device layer (L6) having a transistor (OS2); ([0074], Fig. 1)
a plurality of metallization layers (in L7) above the transistor (OS2); ([0075], Fig. 1) and
a plurality of vias (44 and 24) below and coupled to the transistor (OS2); ([0186]) and
a backside structure (annotated below) below the plurality of vias (44 and 24) of the device layer (L6), the backside structure (L4-L5) including a memory layer (L5) coupled to the transistor (OS2) by the plurality of vias (44 and 24). (Fig. 1 and 5A)
PNG
media_image1.png
769
683
media_image1.png
Greyscale
Yamazaki does not disclose:
a plurality of nanowire-based select transistors
However, Haratipour discloses:
a plurality of nanowire-based select transistors (110), ([0032], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki and Haratipour to have a plurality of nanowire-based select transistors because they are “promising alternatives to transistors with planar architecture.” (Haratipour, [0032])
Regarding claim 7, Yamazaki discloses the integrated circuit structure of claim 6, wherein the memory layer (L5) comprises a plurality of capacitor structures (C0). ([0060], Fig. 1)
Regarding claim 8, Yamazaki discloses the integrated circuit structure of claim 7. Yamazaki does not disclose wherein the plurality of capacitor structures is a ferroelectric capacitor array.
However, Haratipour discloses:
the plurality of capacitor structures (120) is a ferroelectric capacitor array ([0051], Fig. 4).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki and Haratipour for the plurality of capacitor structures is a ferroelectric capacitor array because “FE memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, FE memories have the potential to be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology.” (Haratipour, [0016])
Regarding claim 9, Yamazaki discloses the integrated circuit structure of claim 6. Yamazaki does not disclose wherein the memory layer comprises a plurality of magnetic random access memory devices.
However, Haratipour discloses:
the memory layer (labeled 220 in Fig. 2) comprises a plurality of magnetic random access memory devices. ([0115], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki and Haratipour for the memory layer comprises a plurality of magnetic random access memory devices because it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987). See MPEP 2144. Furthermore, “FE memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, FE memories have the potential to be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology.” (Haratipour, [0016])
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 20170033109 A1) in view of Haratipour et al. (US 20210398993 A1) as applied to claims 1 and 6 above, and further in view of Sharma et al. (US 20200411078 A1).
Regarding claim 5, Yamazaki in view of Haratipour disclose the integrated circuit structure of claim 1. Yamazaki in view of Haratipour do not disclose wherein the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor).
However, Sharma discloses:
the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) (130). ([0023], [0050]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki, Haratipour and Sharma for the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) in order to “enable a memory density improvement by including multiple layers of memory cell arrays.” (Sharma, [0021])
Regarding claim 10, Yamazaki in view of Haratipour disclose the integrated circuit structure of claim 6. Yamazaki in view of Haratipour do not disclose wherein the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor).
However, Sharma discloses:
the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) (130). ([0023], [0050]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yamazaki, Haratipour and Sharma for the backside structure further comprises a non-memory metal-insulator-metal (MIM capacitor) in order to “enable a memory density improvement by including multiple layers of memory cell arrays.” (Sharma, [0021])
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US 20210398993 A1) in view of Yamazaki (US 20170033109 A1).
Regarding claim 11, Haratipour discloses a computing device (2400), comprising:
a board ([0113], Fig. 12); and
a component ([0113]) coupled to the board ([0113]), the component ([0113]) including an integrated circuit structure (2100),
and a plurality of fin-based select transistors (110), ([0032], Fig. 4)
Haratipour does not disclose:
a front side structure comprising: a device layer having a plurality of fin-based select transistors;
a plurality of metallization layers above the plurality of fin-based select transistors; and
a plurality of vias below and coupled to the plurality of fin-based select transistors; and
a backside structure below the plurality of vias of the device layer, the backside structure including a memory layer coupled to the plurality of fin-based select transistors by the plurality of vias.
However, Yamazaki discloses:
a front side structure (annotated below) comprising:
a device layer (L6) having a transistor (OS2); ([0074], Fig. 1)
a plurality of metallization layers (in L7) above the transistor (OS2); ([0075], Fig. 1) and
a plurality of vias (44 and 24) below and coupled to the transistor (OS2); ([0186]) and
a backside structure (annotated below) below the plurality of vias (44 and 24) of the device layer (L6), the backside structure (L4-L5) including a memory layer (L5) coupled to the transistor (OS2) by the plurality of vias (44 and 24). (Fig. 1 and 5A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Haratipour and Yamazaki to have a front side structure comprising: a device layer having a plurality of fin-based select transistors; a plurality of metallization layers above the plurality of fin-based select transistors; and a plurality of vias below and coupled to the plurality of fin-based select transistors; and a backside structure below the plurality of vias of the device layer, the backside structure including a memory layer coupled to the plurality of fin-based select transistors by the plurality of vias in order to “provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with a small area. Another object of one embodiment of the present invention is to provide a novel semiconductor device.” (Yamazaki, [0007])
Regarding claim 12, Haratipour discloses the computing device of claim 11, further comprising: a memory (2404) coupled to the board ([0113]). ([0115], Fig. 12)
Regarding claim 13, Haratipour discloses the computing device of claim 11, further comprising: a communication chip (2412) coupled to the board ([0113]). ([0116], Fig. 12)
Regarding claim 14, Haratipour discloses the computing device of claim 11, wherein the component ([0113]) is a packaged integrated circuit die (2100). ([0112], Fig. 12)
Regarding claim 15, Haratipour discloses the computing device of claim 11, wherein the component ([0113]) is selected from the group consisting of a processor, a communications chip, and a digital signal processor. ([0112]- [0115], Fig. 12)
Regarding claim 16, Haratipour discloses a computing device (2400), comprising:
a board ([0113], Fig. 12); and
a component ([0113]) coupled to the board ([0113]), the component ([0113]) including an integrated circuit structure (2100),
and a plurality of nanowire-based select transistors (110), ([0032], Fig. 4)
Haratipour does not disclose:
a front side structure comprising: a device layer having a plurality of nanowire-based select transistors;
a plurality of metallization layers above the plurality of nanowire-based select transistors; and
a plurality of vias below and coupled to the plurality of nanowire-based select transistors; and
a backside structure below the plurality of vias of the device layer, the backside structure including a memory layer coupled to the plurality of nanowire-based select transistors by the plurality of vias.
However, Yamazaki discloses:
a front side structure (annotated below) comprising:
a device layer (L6) having a transistor (OS2); ([0074], Fig. 1)
a plurality of metallization layers (in L7) above the transistor (OS2); ([0075], Fig. 1) and
a plurality of vias (44 and 24) below and coupled to the transistor (OS2); ([0186]) and
a backside structure (annotated below) below the plurality of vias (44 and 24) of the device layer (L6), the backside structure (L4-L5) including a memory layer (L5) coupled to the transistor (OS2) by the plurality of vias (44 and 24). (Fig. 1 and 5A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Haratipour and Yamazaki to have a front side structure comprising: a device layer having a plurality of nanowire-based select transistors; a plurality of metallization layers above the plurality of nanowire-based select transistors; and a plurality of vias below and coupled to the plurality of nanowire-based select transistors; and a backside structure below the plurality of vias of the device layer, the backside structure including a memory layer coupled to the plurality of nanowire-based select transistors by the plurality of vias in order to “provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with a small area. Another object of one embodiment of the present invention is to provide a novel semiconductor device.” (Yamazaki, [0007])
Regarding claim 17, Haratipour discloses the computing device of claim 16, further comprising: a memory (2404) coupled to the board ([0113]). ([0115], Fig. 12)
Regarding claim 18, Haratipour discloses the computing device of claim 16, further comprising: a communication chip (2412) coupled to the board ([0113]). ([0116], Fig. 12)
Regarding claim 19, Haratipour discloses the computing device of claim 16, wherein the component ([0113]) is a packaged integrated circuit die (2100). ([0112], Fig. 12)
Regarding claim 20, Haratipour discloses the computing device of claim 16, wherein the component ([0113]) is selected from the group consisting of a processor, a communications chip, and a digital signal processor. ([0112]- [0115], Fig. 12)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Goto et al. (US 20210343787 A1) discloses a memory device with FinFET/nanowire devices [0030], ferroelectric capacitors/MIM capacitors [0020] as a MRAM [0020] but does not disclose all the limitations as required by the claim.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897