Prosecution Insights
Last updated: April 19, 2026
Application No. 18/088,669

DYNAMIC VIEW OF DEBUGGING STATE

Non-Final OA §102§103
Filed
Dec 26, 2022
Examiner
NAHAR, QAMRUN
Art Unit
2199
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
98%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
612 granted / 696 resolved
+32.9% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
15 currently pending
Career history
711
Total Applications
across all art units

Statute-Specific Performance

§101
18.6%
-21.4% vs TC avg
§103
33.0%
-7.0% vs TC avg
§102
28.3%
-11.7% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 696 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 have been examined. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-9, 11-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eidson (US 2020/0133825 A1). Per Claim 1: Eidson teaches: - a processor configured to track debugging actions performed to a software system via a runtime environment of the debugging actions, identify one or more debugging attributes of an object of the software system based on the tracked debugging actions performed to the software system, generate a window which includes details of the one or more identified debugging attributes of the object, and display the window which includes the details of the one or more identified debugging attributes via a user interface of a debugging program ([0034] A processor, such as the processor 112, the processor 122 or a processor of a computing device 130, then executes the selected node using the variables input by the user or default variables. (Step 730). During execution of the node a processor may capture an execution log of the execution of the application and store the log in a memory. (Step 740). ... [0035] The graphical programming debugger 121 then extracts, from the execution log, debugging information associated with the executed node. (Step 750). The extracted execution log, along with the screen related to the node are then displayed to the user. (Step 760). Because the execution log is displayed along with the screen associated with the node, the user can more easily locate and correct bugs in the application. The graphical programming debugger 121 then extracts then returns to Step 720 to await the next selection of a node to be executed. As discussed above, the user may go forwards and backwards through the application, allowing the user to see how each node changes variables, stacks and the like, giving the user a better appreciate of how each node is affecting the program and how each node may be contributing to an error in the application.; see also [0030-0033]). Per Claim 3: Eidson teaches: - wherein the processor is configured to identify a rate of creation of the object over a predetermined period of time based on the tracked debugging actions performed to the software system and display the identified rate of creation of the object via the window (e.g. see abstract and pg. 4, claims 1 and 6). Per Claim 4: Eidson teaches: - wherein the processor is configured to identify a rate of destruction of the object over a predetermined period of time based on the tracked debugging actions performed to the software system and display the identified rate of destruction of the object via the window (e.g. see abstract and pg. 4, claims 1 and 6). Per Claim 5: Eidson teaches: - wherein the processor is configured to identify a rate of invocation of a method of the object over a predetermined period of time based on the tracked debugging actions performed to the software system and display the identified rate of the method calls to the method of the object via the window (e.g. see abstract and pg. 4, claims 1 and 6). Per Claim 6: Eidson teaches: - wherein the processor is further configured to predict an estimated end of life of the object and display the predicted estimate of the end of life of the object via the window (e.g. see pg. 4, claims 5 and 6). Per Claim 7: Eidson teaches: - wherein the processor is configured to identify a value of a debugging attribute of each respective object from among a plurality of objects of the software system over a predetermined period of time based on the tracked debugging actions and display the value of the debugging attribute of each respective object from among the plurality of objects via the window (par. 0033-0035). Per Claim 8: Eidson teaches: - wherein the processor is further configured to determine an age of the object based on the tracked debugging actions and display the determined age of the object via the window (e.g. see abstract and pg. 4, claim 5). Per Claims 9 & 11-16: These are method versions of the claimed apparatus discussed above (claims 1 and 3-8, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, these claims are also anticipated by Eidson. Per Claims 17 & 19-20: These are medium versions of the claimed apparatus discussed above (claims 1, 3 and 5, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, these claims are also anticipated by Eidson. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eidson (US 2020/0133825 A1) in view of Kasman (US 2008/0127119). Per Claim 2: The rejection of claim 1 is incorporated, and further, Eidson does not explicitly teach wherein the processor is configured to record debugging actions performed by a plurality of users of the software system and identify the one or more attributes of the object of the software system based on the recorded debugging actions of the plurality of users. However, Kasman teaches wherein the processor is configured to record debugging actions performed by a plurality of users of the software system and identify the one or more attributes of the object of the software system based on the recorded debugging actions of the plurality of users (par. 0031). It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Eidson to include wherein the processor is configured to record debugging actions performed by a plurality of users of the software system and identify the one or more attributes of the object of the software system based on the recorded debugging actions of the plurality of users using the teaching of Kasman. The modification would be obvious because one of ordinary skill in the art would be motivated to provide dynamic debugging of software (Kasman, par. 0004). Per Claim 10: This is a method version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious. Per Claim 18: This is a medium version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lamda (US 2023/0333966) teaches a method for displaying debugging attributes to users. Any inquiry concerning this communication or earlier communications from the examiner should be directed to QAMRUN NAHAR whose telephone number is (571)272-3730. The examiner can normally be reached Monday - Friday 8-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached on (571)272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QAMRUN NAHAR/Primary Examiner, Art Unit 2199
Read full office action

Prosecution Timeline

Dec 26, 2022
Application Filed
Oct 20, 2023
Response after Non-Final Action
Jan 22, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12602227
A METHOD FOR ASSESSING QUALITY OF OPEN SOURCE PROJECTS
2y 5m to grant Granted Apr 14, 2026
Patent 12602219
INFORMATION PROCESSING APPARATUS CAPABLE OF PREVENTING DELAY OF EXECUTION OF PERIODICALLY EXECUTED PROCESSING, METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM
2y 5m to grant Granted Apr 14, 2026
Patent 12602482
Systems and methods for updating a network appliance
2y 5m to grant Granted Apr 14, 2026
Patent 12596537
GENERALIZED INTERMEDIATE AND LOWER LEVEL SOURCE CODE REPRESENTATIONS FOR STATIC APPLICATION SECURITY TESTING
2y 5m to grant Granted Apr 07, 2026
Patent 12596533
SELECTING A CUSTOM FUNCTION FROM AVAILABLE CUSTOM FUNCTIONS TO BE ADDED INTO A PLAYBOOK
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
98%
With Interview (+9.9%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 696 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month