Prosecution Insights
Last updated: April 19, 2026
Application No. 18/088,908

APPARATUS, SYSTEM, AND METHOD FOR INTEGRATING PASSIVE ELEMENTS INTO ELECTRONIC BRIDGE COMPONENTS

Non-Final OA §103
Filed
Dec 27, 2022
Examiner
CLINTON, EVAN GARRETT
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
3 (Non-Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
483 granted / 549 resolved
+20.0% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
27 currently pending
Career history
576
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
56.7%
+16.7% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 549 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5-6, 8-12, and 19 are rejected under 35 U.S.C. 103 as being obvious over Foo et al. (U.S. Publication No. 2024/0063148) in view of Xie et al. (U.S. Publication No. 2020/0395300) Regarding claim 1, Foo teaches a bridge device comprising: a bridge component (Fig. 1 and 2, bridge 102/202) comprising a semiconductor material (paragraph [0036], silicon); at least one routing layer (Fig. 2, routing layer 230) of the bridge component dimensioned to electronically couple a first die (first die 252) and at least one second die (second die 254); and at least one passive element (Fig. 1, capacitor made up of 114/116/118) located above and/or below the first die (Fig. 2, below die), integrated into the bridge component and configured to store an electrical charge (inherent that the function of a capacitor is charge storage, see also paragraph [0059]). Foo does not specifically teach the capacitor delivers the stored electrical charge to the first die along a vertical plane from the at least one passive element to the first die using at least one via through at least one layer of the bridge component configured to allow the first die to draw power vertically through the at least one via from the at least one passive element of the bridge component. However, Xie teaches a similar package wherein the capacitor (Xie Fig. 3, capacitor 380) delivers the stored electrical charge to the first die along a vertical plane from the at least one passive element to the first die using at least one via through at least one layer of the bridge component (see Xie Fig. 3, capacitor 380 is connected to die 114-1 through a vertical plane/via that goes through at least one layer of the bridge, via not specifically labeled but shown in Fig. 3) configured to allow the first die to draw power vertically through the at least one via (see Fig. 3 and paragraph [0034], power planes 219 shown above and below the capacitor and connected to the capacitor and the via that is connected to the die) from the at least one passive element of the bridge component (capacitor is a decoupling capacitor, see paragraph [0071], and therefore by definition delivers power to the die through the capacitor). It would have been obvious to a person of skill in the art at the time of the effective filing date that the dies could have had vertical vias coupled to the bridge capacitor to draw power because this allows for the capacitor to function as a decoupling capacitor with a short route between the die and power/ground. Regarding claim 2, Foo teaches the bridge device of claim 1, wherein the routing layer is disposed on a side of the bridge device facing the first die and the second die (Fig. 2). Regarding claim 3, Foo teaches the bridge device of claim 1, further comprising at least one alternative passive element (see Fig. 1, contains multiple separate capacitors). Regarding claim 5, Foo teaches the bridge device of claim 1, wherein the passive element configured to store the electrical charge comprises an integrated capacitor (Fig. 1). Regarding claim 6, Foo teaches the bridge device of claim 5, wherein the integrated capacitor provides the stored electrical charge, via an integrated circuit drawing a current, to at least one of: the first die (see Fig. 1-2, electrode of capacitor is directly connected to first and second dies); the second die; or a different element integrated into the bridge component. Regarding claim 8, Foo teaches the bridge device of claim 7, wherein the passive element is configured to increase a decoupling capacitance in an area of the bridge device around the passive element and at least one of: the area of the first die overlapping the bridge device; or the area of the second die overlapping the bridge device (paragraph [0014]). Regarding claim 9, Foo teaches the bridge device of claim 7, further comprising a second passive element integrated into the bridge component and configured to store the electrical charge, wherein the second passive element is positioned on the bridge device between the area of the first die overlapping the bridge device and the area of the second die overlapping the bridge device (see Fig. 1 and 2, multiple capacitors, each under a separate die). Regarding claim 10, Foo teaches the bridge device of claim 1, wherein the bridge device comprises at least one of: a passive bridge (see Fig. 1, no active devices, furthermore it is inherent that it is either active or passive because those are the only two options); or an active bridge. Regarding claim 11, Foo teaches the bridge device of claim 10, wherein the passive element of the active bridge is configured to provide the stored electrical charge to at least one active element of the active bridge (claim 10 recites passive and active bridges in the alternative, and therefore all of claim 11 is also in the alternative because it further limits the optional “active bridge” portion of claim 10; i.e. no limitations of claim 11 are necessary as long as a passive bridge is taught by the prior art). Regarding claim 12, Foo teaches the bridge device of claim 1, further comprising at least one through-silicon via (TSV) (see Fig. 3A, TSV 314) embedded in the bridge component such that the TSV conducts the electrical charge through at least one layer of the bridge device (see Fig. 3A) and wherein the TSV is coupled to the surface of the first die (see paragraphs [0072]-[0073]). Regarding claim 19, Foo teaches a method of manufacturing comprising: coupling a first die (Fig. 2, first die 252) to at least one substrate (substrate 240) such that the substrate delivers an electrical charge to the first die (Fig. 2); coupling a second die (second die 254) to the substrate such that the substrate delivers the electrical charge to the second die (Fig. 2); integrating at least one passive element (capacitor 214/216/218) into a bridge device (bridge 202) below or above the die (see Fig. 2, below die), wherein the passive element is configured to store the electrical charge (paragraph [0059] and Fig. 2) and deliver the stored electrical charge from the at least one passive element to the die (see paragraphs [0053]-[0054]); and electronically coupling the bridge device to the first die and the second die such that the passive element is electronically coupled to at least one of: the first die; or the second die (Fig. 2). Foo does not specifically teach the charge is delivered along a vertical plane. However, Xie teaches a similar package including a vertical via (Xie Fig. 3, vias not labeled, but seen through capacitor 380) that delivers a charge from the capacitor (380) to the die (see Fig. 3 and paragraph [0034]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the dies could have had vias coupled to the bridge capacitor to draw power because this allows for the capacitor to function as a decoupling capacitor with a short route between the die and power/ground. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Foo in view of Xie, further in view of Jain et al. (U.S. Publication No. 2019/0304915) Regarding claim 4, Foo teaches the bridge device of claim 3, but does not teach wherein the alternative passive element comprises at least one of: an integrated inductor; an integrated resistor; a transformer; a diode; or a fuse. However, Jain teaches that a bridge can have an embedded capacitor and resistor (see Jain paragraph [0025]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the bridge could have incorporated both a capacitor and a resistor because Jain teaches that this allows for calibration as well as improved EMI and noise characteristics (Jain paragraph [0026]). Response to Arguments Applicant’s arguments with respect to claims 1-19 have been considered but are not persuasive. Applicant argues that Foo teaches an RDL between the capacitor and the die, and therefore cannot have the charge delivered in a vertical plane. However, as shown in Xie Fig. 3, vertical vias can be found stacked in the RDL, therefore allowing for both an RDL and also a vertical via pathway from the capacitor to the dies. It would have been obvious that the RDL of Foo could have modified to a similar RDL to that of Xie in order to reduce the pathway between the capacitor and die, reducing resistance and delays in the signal. Allowable Subject Matter Claims 7 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 7, the prior art, alone or in combination, fails to teach or suggest and wherein a density of passive elements is greater above or below the first die or the second die than between the first die or the second die. Regarding claim 21, the prior art, alone or in combination, fails to teach or suggest wherein a number of the at least one passive elements per square area is greater in a region of the bridge component located below and/or above the first die and/or the at least one second die than in a region of the bridge component located between the first and the at least one second die. Claims 13-18 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claims 13-18, the prior art, alone or in combination, fails to teach or suggest wherein a number of the at least one passive elements per square area is greater in a region of the bridge device located below and/or above the first die and/or the at least one second die than in a region of the device located between the first and the at least one second die. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVAN G CLINTON/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Dec 27, 2022
Application Filed
Jul 11, 2025
Non-Final Rejection — §103
Sep 16, 2025
Interview Requested
Sep 22, 2025
Examiner Interview Summary
Sep 22, 2025
Examiner Interview (Telephonic)
Oct 01, 2025
Response Filed
Oct 17, 2025
Final Rejection — §103
Jan 21, 2026
Request for Continued Examination
Jan 29, 2026
Response after Non-Final Action
Feb 04, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+5.5%)
2y 1m
Median Time to Grant
High
PTA Risk
Based on 549 resolved cases by this examiner. Grant probability derived from career allow rate.

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