DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of diisobutylaminetrisilane, trisilane and PH3 in the reply filed on 11/24/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 4, 6 are withdrawn from consideration as directed to non-electeed species. Claims 1-3, 5, 7-20 are examined on the merits. Claims 7-8 are indicated as withdrawn by the applicant; however, such are examined on the merits to the extent that they read on the elected second Si-Precursor (trisilane).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-13, 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication 20200168455 by Kanemura et al.
Claim 1: Kanemura discloses a method of forming a conformal and continuous crystalline Si film on a surface of a substrate, the method comprising: i) exposing the substrate to a vapor of a first Si-containing precursor under a first temperature (0022); ii) allowing a seed film being formed onto the surface (0022, seed layer); iii) exposing the substrate to a vapor of a second Si-containing precursor and a vapor of a dopant precursor under a second temperature (0027-0029); iv) depositing a doped amorphous Si-containing film onto the seed film by a chemical vapor deposition (CVD) process (0027-0030); and v) annealing the substrate to crystalize the doped amorphous Si-containing film forming the conformal and continuous crystalline Si film on the surface (0030-0032).
Claim 7-9: Kanemura discloses trisilane (0029)
Claim 10: Kanemura discloses PH3 (0029).
Claim 11: Kanemura discloses an amorphous silicon film on the seed layer, which can reasonably conformal as broadly drafted (0027).
Claim 12: Kanemura discloses of 28 nm (0067), a value that anticipates the claim.
Claim 13: Kanemura fails to explicitly disclose the claimed properties of the film; however, as evidenced by claim 1, Kanemura discloses all the same process steps that are claimed and disclosed as being required to achieve the claimed result and thus the results obtained by applicant’s process must necessarily be the same as those obtained by the prior art. Either 1) the applicant and the prior art have different definitions for the claimed terms, or 2) the applicant is using other process steps or parameters that are not shown in the claims.
Claim 15: Kanemura discloses the first temperature as claimed (see 0022, 350C at 0069).
Claim 16: Kanemura discloses the second temperature (0030)
Claim 17: Kanemura discloses a pressure that reads on the claim (0022, 0067)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura taken with US Patent Application Publication 20200035490 by He et al.
Kanemura discloses all that is taught above and discloses amorphous Si by CVD followed by annealing to form polycrystalline Si; however, fails to disclose the air to form the native oxide. However, He, also in the art of forming a polysilicon layer by depositing amorphous Si by CVD followed by annealing (0029, 0034) and discloses forming a native oxide on the surface of the amorphous Si prior to annealing (see 0029-0034) and therefore taking the references collectively it would have been obvious to have modified Kanemura to include the air exposure to form the native oxide as suggested by He prior to the anneal as such is taught by He as providing a benefit for the polysilicon Si formation and to control the oxide formation process.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura taken with US Patent Application Publication 20030036268 by Brabant et al.
Kanemura discloses all that is taught above and discloses amorphous Si by CVD for semiconductor films; however, fails to disclose the precleaning and heating as claimed. However, Brabant, also in the art of coating semiconductors surface prior to CVD deposition, including e.g. amorphous or crystalline silicon (see 0052) and discloses precleaning the substrate with RCA clean process, including SC-1 and HF (0010-0013) and discloses heating the substrate after cleaning to a temperature to remove impurities and desorbs the hydrogen termination (0028) including at a temperature of less than 550 C. Therefore, taking the references collectively it would have been obvious to use the precleaning process of Brabant to prepare the semiconductor substrate for CVD deposition as Brabant discloses such is known and suitable in the art and would provide predictable results, that is a clean semiconductor for CVD deposition.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura taken with US Patent 10,030,038 by Rekken et al.
Kanemura discloses all that is taught above and disclose using amino silane gas, exemplifying diisopropylaminosilane; however, fails to disclose the claimed silane gas. However, Rekken, also in the art of amino silane gases for forming silicon films and discloses known aminosilanes include diisopropylaminotrisilane (column 6, lines 45-68) and discloses compounds that encompass the claimed compound (see e.g. column 4, lines 20-68, isopropyl or iso-butyl as alternative R groups, column 5, lines 25-50). Therefore taking the references collectively and all that is known to one of ordinary skill in the art, it would have been obvious to have utilized the claimed compound with a reasonable expectation of predictable results and to reap the benefits as specifically taught by Rekken (column 1, lines 30-45). Here, using diisopropylaminotrisilane would have been obvious as a known amino silane (and specifically disclosed compound) and using iso-butyl as a substitute for iso-propyl would have been obvious as known substitutes as specifically taught by Rekken.
Claim(s) 7-9, 12, 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura.
Claim 7-9: While the examiner maintains the position as set forth above, Kanemura explicitly discloses using a second silicon source, including trisilane, and therefore using trisilane would have been obvious to one of ordinary skill in the art.
Claims 12, 15-17: While the examiner maintains the Kanemura reference anticipates the claims, the examiner notes that the thickness, temperature and pressure ranges as taught by the prior art are within or overlap the ranges as claimed and thus make obvious such.
Claim 14: Kanemura discloses including an electrical dopant; however, fails to disclose the amount as claimed. However, the amount of impurity inclusion would have been recognized as a result effective variable, directly affecting the film properties and a result of the dopant inclusion (0029), and therefore it would have been obvious to one of ordinary skill in the art to have determined the optimum and desirable amount of dopant, through routine experimentation to deposit the film with the desired properties.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura taken with Rekken et al. as applied above and taken with US Patent Application Publication 20150037970 by Hasebe and US Patent 5242855 by Oguro.
Kanemura and Rekken are applied for the reasons set forth above. As for the seed formation temperature, Kanemura and Rekken fails to disclose 200C as claimed. However, Hasebe, also in the art of silicon forming layers using a seed and vapor deposition discloses seed layer formation temperature that overlaps the range as claimed (see Figure 1 and accompanying text, abstract) and is a result effective variable (figure 4-5 and accompanying text) and therefore taking the references collectively it would have been obvious to use the known and suitable temperature, including 200C, as such would have been obvious in view of the teaching of Hasebe and the temperature of Hasebe encompass the claimed value. Additionally, as Hasebe discloses the seed forming temperature is a result effective variable, determination of such would have been obvious through routine experimentation to deposit the desired seed thickness.
Kanemura discloses and makes obvious trisilane and PH3 doped as outlined above; however, fails to disclose the N2 gas. However, Oguro, also in the art of forming silicon film via CVD, discloses supplying PH3 diluted with N2 and therefore taking the reference collectively it would have been obvious to supply PH3 with N2 as suggested by Oguro with a reasonable expectation of predictable results. The amount of PH3 is would have been recognized as a result effective variable, directly affecting the film properties and a result of the dopant inclusion and Oguro discloses adjusting the doping amount to achieve property adjustment, and therefore it would have been obvious to one of ordinary skill in the art to have determined the optimum and desirable amount of dopant, through routine experimentation to deposit the film with the desired properties.
Temperature of CVD formation and annealing are encompassed by the ranges as taught by Kanemura and thus make obvious such.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura taken with Rekken et al., Hasebe and Oguro as applied above and further with He.
Kanemura taken with Rekken et al., Hasebe and Oguro discloses all that is taught above and discloses amorphous Si by CVD followed by annealing to form polycrystalline Si; however, fails to disclose the air to form the native oxide. However, He, also in the art of forming a polysilicon layer by depositing amorphous Si by CVD followed by annealing (0029, 0034) and discloses forming a native oxide on the surface of the amorphous Si prior to annealing (see 0029-0034) and therefore taking the references collectively it would have been obvious to have modified Kanemura to include the air exposure to form the native oxide as suggested by He prior to the anneal as such is taught by He as providing a benefit for the polysilicon Si formation and to control the oxide formation process.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura taken with Rekken et al., Hasebe and Oguro as applied above taken with Brabant.
Kanemura discloses all that is taught above and discloses amorphous Si by CVD for semiconductor films; however, fails to disclose the precleaning and heating as claimed. However, Brabant, also in the art of coating semiconductors surface prior to CVD deposition, including e.g. amorphous or crystalline silicon (see 0052) and discloses precleaning the substrate with RCA clean process, including SC-1 and HF (0010-0013) and discloses heating the substrate after cleaning to a temperature to remove impurities and desorbs the hydrogen termination (0028) including at a temperature of less than 550 C. Therefore, taking the references collectively it would have been obvious to use the precleaning process of Brabant to prepare the semiconductor substrate for CVD deposition as Brabant discloses such is known and suitable in the art and would provide predictable results, that is a clean semiconductor for CVD deposition. The heating temperature overlaps the value as claimed and thus makes obvious such. Additionally, due to the comprising language, as the temperature of the substrate increases, it would comprise heating at 400C as claimed. Finally, the prior art disclose the temperature is a result effective variable to provide the benefits of desorption of the terminations and therefore determination of the optimum temperature through routine experimentation would have been obvious to one of ordinary skill in the art to achieve predictable and desired results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID P TUROCY whose telephone number is (571)272-2940. The examiner can normally be reached Mon, Tues, Thurs, and Friday, 7:00 a.m. to 5:30 p.m.
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/DAVID P TUROCY/Primary Examiner, Art Unit 1718