Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, the term “target voltage” in line 7 is not adequately defined in the specification or the claim. It is impossible to know when/if a static voltage is less than a target voltage. Para [0029] of the spec defines the target voltage as depending on a process technology characterization to ensure latent defects are accelerated properly to be screened by subsequent tests but this definition does not provide a way to assess the metes and bounds of the voltage levels as claimed, and seems to indicate the target voltage can vary depending on what is being tested or the type of test being performed. Thus, the broadest reasonable interpretation, based on the specification, is the target voltage can be any voltage that should not be exceeded during testing, which since this range of voltages is not constrained, is indefinite. For the purposes of compact prosecution, the examiner will interpret this limitation such that any prior art that considers varying the static voltage will read on the claim.
Regarding Claim 5, the term “target voltage” in line 1 is not adequately defined in the spec or the claim. It is impossible to know when/if a static voltage is less than a target voltage. Para [0029] of the spec defines the target voltage as depending on a process technology characterization to ensure latent defects are accelerated properly to be screened by subsequent tests but this definition does not provide a way to assess the metes and bounds of the voltage levels as claimed, and seems to indicate the target voltage can vary depending on what is being tested or the type of test being performed. Thus, the broadest reasonable interpretation, based on the specification is the target voltage can be any voltage that should not be exceeded during testing, which since this range of voltages is not constrained, is indefinite. For the purposes of compact prosecution, the examiner will interpret this limitation such that any prior art that considers varying the static voltage will read on the claim.
Regarding Claim 9, the term “target voltage” in line 8 is not adequately defined in the spec or the claim. It is impossible to know when/if a static voltage is less than a target voltage. Para [0029] of the spec defines the target voltage as depending on a process technology characterization to ensure latent defects are accelerated properly to be screened by subsequent tests but this definition does not provide a way to assess the metes and bounds of the voltage levels as claimed, and seems to indicate the target voltage can vary depending on what is being tested or the type of test being performed. Thus, the broadest reasonable interpretation, based on the specification is the target voltage can be any voltage that should not be exceeded during testing, which since this range of voltages is not constrained, is indefinite. For the purposes of compact prosecution, the examiner will interpret this limitation such that any prior art that considers varying the static voltage will read on the claim.
Regarding Claim 13, the term “target voltage” in line 1 is not adequately defined in the spec or the claim. It is impossible to know when/if a static voltage is less than a target voltage. Para [0029] of the spec defines the target voltage as depending on a process technology characterization to ensure latent defects are accelerated properly to be screened by subsequent tests but this definition does not provide a way to assess the metes and bounds of the voltage levels as claimed, and seems to indicate the target voltage can vary depending on what is being tested or the type of test being performed. Thus, the broadest reasonable interpretation, based on the specification is the target voltage can be any voltage that should not be exceeded during testing, which since this range of voltages is not constrained, is indefinite. For the purposes of compact prosecution, the examiner will interpret this limitation such that any prior art that considers varying the static voltage will read on the claim.
Regarding Claim 17, the term “target voltage” in line 9 is not adequately defined in the spec or the claim. It is impossible to know when/if a static voltage is less than a target voltage. Para [0029] of the spec defines the target voltage as depending on a process technology characterization to ensure latent defects are accelerated properly to be screened by subsequent tests but this definition does not provide a way to assess the metes and bounds of the voltage levels as claimed, and seems to indicate the target voltage can vary depending on what is being tested or the type of test being performed. Thus, the broadest reasonable interpretation, based on the specification is the target voltage can be any voltage that should not be exceeded during testing, which since this range of voltages is not constrained, is indefinite. For the purposes of compact prosecution, the examiner will interpret this limitation such that any prior art that considers varying the static voltage will read on the claim.
Regarding Claims 2-8, 10-16 and 18-20, These claims stand rejected for incorporating and reciting the above rejected subject matter of their respective parent claim(s) and therefore stand rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (US-20210199710-A1).
Regarding Claim 1, He teaches A method for testing an integrated circuit for defects, the method comprising:
applying a nominal voltage (Fig 4: first voltage level, 200) to the integrated circuit (Fig 1: IC, 112) for a first time period (Refer to annotated Figure 4 of He);
applying a dynamic voltage (Fig 4: third voltage level, 424) greater than the nominal voltage (Para [0046] teaches the second voltage level, 422, may be 3 times higher than the first voltage level, 200, and further teaches the third voltage level, 424, maybe 0.9 times the second voltage level, 422. Therefore Para [0046] teaches the third voltage level may be greater than the nominal or first voltage level, 200) to the integrated circuit for a second time period after the first time period (Refer to annotated Figure 4 of He);
applying a static voltage (Fig 4: second voltage level, 422) greater than the dynamic voltage to the integrated circuit for a third time period after the second time period (Refer to annotated Figure 4 of He), wherein the static voltage is a target static voltage less than a target voltage (Para [0028] teaches the stress signal may vary based on testing requirements and the defective-parts-per-million (DPPM)); and
applying the dynamic voltage to the integrated circuit during a fourth time period after the third time period (Refer to annotated Figure 4 of He).
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Annotated Figure 4 of He
Regarding Claims 2 & 3, He teaches The method of claim 1, wherein the second time period and the fourth time period are activity time periods;
wherein performance of at least one integrated circuit test occurs during the activity time periods (Fig 7 shows in steps 716 and 718 that the ramping up and down of voltages is done in order to test the IC. The times periods being toggle between are described in at least Para [0049] as energizing the IC and causing it to change or toggle states, therefore activity happens during these time periods).
Regarding Claim 4, He teaches wherein the third time period is an idle time period (Para [0024] of the instant application refers to the idle time as when a static stress is applied to the IC where the voltage appears to be held constant based on the graph in Fig 1 of the instant application. Para [0028] of the reference teaches the voltage, 222 (or 422), is the stress voltage, which it also shows to be held constant in Fig 4, during the time period).
Regarding Claim 5, He teaches The method of claim 1, wherein the target voltage is not applied to the integrated circuit during a test for defects of the integrated circuit (From Figure 4 no voltages other than the nominal, static and dynamic are applied during the test).
Regarding Claim 7, He teaches The method of claim 1, further comprising: applying the static voltage to the integrated circuit during a fifth time period after the fourth time period (Refer to annotated Fig 4 of He).
Regarding Claim 8, He teaches The method of claim 1, wherein the second time period and the fourth time period are different in duration (Fig 4 shows a difference in duration of the second and fourth time periods).
Regarding Claim 9, He teaches A device for testing an integrated circuit for defects, the device (Fig 1: signal generator, 102) comprising a voltage source configured to:
apply a nominal voltage (Fig 4: first voltage level, 200) to the integrated circuit (Fig 1: IC, 112) for a first time period (Refer to annotated Figure 4 of He);
apply a dynamic voltage (Fig 4: third voltage level, 424) greater than the nominal voltage (Para [0046] teaches the second voltage level, 422, may be 3 times higher than the first voltage level, 200, and further teaches the third voltage level, 424, maybe 0.9 times the second voltage level, 422. Therefore Para [0046] teaches the third voltage level may be greater than the nominal or first voltage level, 200) to the integrated circuit for a second time period after the first time period (Refer to annotated Figure 4 of He);
apply a static voltage (Fig 4: second voltage level, 422) greater than the dynamic voltage to the integrated circuit for a third time period after the second time period (Refer to annotated Figure 4 of He), wherein the static voltage is a target static voltage less than a target voltage (Para [0028] teaches the stress signal may vary based on testing requirements and the defective-parts-per-million (DPPM)); and
apply the dynamic voltage to the integrated circuit during a fourth time period after the third time period (Refer to annotated Figure 4 of He).
Regarding Claim 10 and 11, He teaches The device of claim 9, wherein the second time period and the fourth time period are activity time periods;
wherein performance of at least one integrated circuit test occurs during the activity time periods (Fig 7 shows in steps 716 and 718 that the ramping up and down of voltages is done in order to test the IC. The times periods being toggle between are described in at least Para [0049] as energizing the IC and causing it to change or toggle states, therefore activity happens during these time periods).
Regarding Claim 12, He teaches The device of claim 9, wherein the third time period is an idle time period (Para [0024] of the instant application refers to the idle time as when a static stress is applied to the IC where the voltage appears to be held constant based on the graph in Fig 1 of the instant application. Para [0028] of the reference teaches the voltage, 222 (or 422), is the stress voltage, which it also shows to be held constant in Fig 4, during the time period).
Regarding Claim 13, He teaches The device of claim 9, wherein the target voltage is not applied to the integrated circuit during a test for defects of the integrated circuit (From Figure 4 no voltages other than the nominal, static and dynamic are applied during the test).
Regarding Claim 15, He teaches The device of claim 9, wherein the voltage source is further configured to: apply the static voltage to the integrated circuit during a fifth time period after the fourth time period (Refer to annotated Fig 4 of He).
Regarding Claim 16, He teaches The device of claim 9, wherein the second time period and the fourth time period are different in duration (Fig 4 shows a difference in duration of the second and fourth time periods).
Regarding Claim 17, He teaches A system for testing an integrated circuit for defects, the system comprising:
the integrated circuit (Fig 1: IC, 112); and
a voltage source configured to:
apply a nominal voltage (Fig 4: first voltage level, 200) to the integrated circuit (Fig 1: IC, 112) for a first time period (Refer to annotated Figure 4 of He);
apply a dynamic voltage (Fig 4: third voltage level, 424) greater than the nominal voltage (Para [0046] teaches the second voltage level, 422, may be 3 times higher than the first voltage level, 200, and further teaches the third voltage level, 424, maybe 0.9 times the second voltage level, 422. Therefore Para [0046] teaches the third voltage level may be greater than the nominal or first voltage level, 200) to the integrated circuit for a second time period after the first time period (Refer to annotated Figure 4 of He);
apply a static voltage (Fig 4: second voltage level, 422) greater than the dynamic voltage to the integrated circuit for a third time period after the second time period (Refer to annotated Figure 4 of He), wherein the static voltage is a target static voltage less than a target voltage (Para [0028] teaches the stress signal may vary based on testing requirements and the defective-parts-per-million (DPPM)); and
apply the dynamic voltage to the integrated circuit during a fourth time period after the third time period (Refer to annotated Figure 4 of He).
Regarding Claim 18 and 19, He teaches The system of claim 17, wherein the second time period and the fourth time period are activity time periods;
wherein performance of at least one integrated circuit test occurs during the activity time periods (Fig 7 shows in steps 716 and 718 that the ramping up and down of voltages is done in order to test the IC. The times periods being toggle between are described in at least Para [0049] as energizing the IC and causing it to change or toggle states, therefore activity happens during these time periods).
Regarding Claim 20, He teaches The system of claim 17, wherein the third time period is an idle time period (Para [0024] of the instant application refers to the idle time as when a static stress is applied to the IC where the voltage appears to be held constant based on the graph in Fig 1 of the instant application. Para [0028] of the reference teaches the voltage, 222 (or 422), is the stress voltage, which it also shows to be held constant in Fig 4, during the time period).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over He.
Regarding Claims 6 and 14, He does not explicitly teach wherein the first time period, the second time period, the third time period, and the fourth time period are contiguous time periods. However, the difference in the prior art and in the instant application is that the dynamic voltage is applied immediately following the nominal, this is what allows the time periods as claimed to be contiguous. The prior art teaches applying the static voltage (second voltage level, 422) after the nominal. However, in both the prior art and the instant application it is the swapping between the static voltage and dynamic voltage levels where the main concept behind the invention lies. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to begin with the dynamic voltage level, there being only a finite number of options to choose from, then switch to the higher voltage (stress). As stated before, beginning with the dynamic voltage level will make the time periods as claimed contiguous. One of ordinary skill would have a reasonable expectation of success by beginning with the dynamic voltage level as the main purpose of the inventive concept lies in the switching between the voltage levels and not in which voltage level begins the switching.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMIAH J BARRON whose telephone number is (571)272-0902. The examiner can normally be reached M-F 09:30-17:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEREMIAH J BARRON/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858