Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
In response to election/restriction, applicant elected claims 1-14 without traverse.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alur et al. (US 10,163,798, hereinafter Alur).
With respect to claim 1, Alur discloses a semiconductor device (Fig. 6), comprising: two or more semiconductor dies (370 & 372) coupled to a substrate (606 & 374), the substrate including a number of substrate traces (114, 118, 122 and 126 of Fig. 1F) and a number of first vertical connections (112, 116, 120 and 124 of Fig. 1F);
an interconnect bridge (640, 148, 156, 386 and 388 of Fig. 6) connected between the two or more semiconductor dies (Col. 4; lines 63-67; the bridge die 140/640 provides a communication bridge between dice 370 & 372), the interconnect bridge including:
a number of lateral traces (148); a number of second vertical connections (386 & 388) coupled between the number of lateral traces (Fig. 6) and the two or more semiconductor dies (Fig. 6); and a layer (156) including tin at an interface between the lateral traces and the number of second vertical connections (Col. 4; lines 10-15; Sn or NiSn bond layer 156).
With respect to claim 2, Alur discloses wherein the interconnect bridge is at least partially embedded in the substrate (Col. 4; lines 8-15; lines 54-61).
With respect to claim 6, Alur discloses including tin at an interface between the number of substrate traces and the first vertical connections (Col. 4; lines 10-15; Sn or NiSn bond layer).
With respect to claim 7, Alur discloses nickel, palladium and gold at an interface between the number of substrate traces and the first vertical connections (Col. 4; lines 1-7).
With respect to claim 8, Alur discloses solder at an interface between the number of second vertical connections and the two or more semiconductor dies (Col. 10; lines 50-52 – solder paste).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Alur in view of Cheah et al. (US 2021/0384130, hereinafter Cheah).
With respect to claim 3, Alur discloses the semiconductor device of claim 1.
Alur does not explicitly disclose one or more capacitors coupled to the substrate at the first vertical connections.
In an analogous art, Cheah discloses one or more capacitors coupled to the substrate at the first vertical connections (Para 0048; 0069). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur’s device by having Cheah’s disclosure in order to store and release electrical energy to stabilize voltage and manage power in a semiconductor device.
With respect to claim 4, Alur/Cheah discloses the semiconductor device of claim 3.
Alur does not explicitly disclose wherein the one or more capacitors includes a die side capacitor.
In an analogous art, Cheah discloses wherein the one or more capacitors includes a die side capacitor (Para 0048 and 0081). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur’s device by having Cheah’s disclosure in order to store and release electrical energy to stabilize voltage and manage power in a semiconductor device.
With respect to claim 5, Alur/Cheah discloses the semiconductor device of claim 4.
Alur does not explicitly disclose wherein the one or more capacitors includes a land side capacitor.
In an analogous art, Cheah discloses wherein the one or more capacitors includes a land side capacitor (Para 0048 and 0081). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur’s device by having Cheah’s disclosure in order to store and release electrical energy to stabilize voltage and manage power in a semiconductor device.
Claims 9-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Alur in view of Paital et al. (US 2020/0343049, hereinafter Pailtal).
With respect to claim 9, Alur discloses a semiconductor device (Fig. 6), comprising: two or more semiconductor dies (370 & 372) coupled to a substrate (606 & 374), the substrate including a number of substrate traces (114, 118, 122 and 126 of Fig. 1F) and a number of first vertical connections (112, 116, 120 and 124 of Fig. 1F); an interconnect bridge (640, 148, 156, 386 and 388 of Fig. 6) connected between the two or more semiconductor dies (Col. 4; lines 63-67; the bridge die 140/640 provides a communication bridge between dice 370 & 372), the interconnect bridge including:
a number of lateral traces (148); a number of second vertical connections (386 & 388) coupled between the number of lateral traces (Fig. 6) and the two or more semiconductor dies (Fig. 6); and a layer (156) including tin at an interface between the number of lateral traces and the second vertical connections (Col. 4; lines 10-15; Sn or NiSn bond layer 156).
Alur does not explicitly disclose one or more capacitors connected to the substrate through the number of first vertical connections; and a bridge fiducial marker.
In an analogous art, Paital discloses one or more capacitors coupled to the substrate through the number of first vertical connections (Para 0089-0090; capacitors); and a bridge fiducial marker (Para 0066; fiducial marks). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur’s device by having Pailtal’s disclosure in order to store and release electrical energy to stabilize voltage and manage power in a semiconductor device.
With respect to claim 10, Alur/Paital discloses the semiconductor device of claim 9.
Alur does not explicitly disclose a substrate fiducial marker.
In an analogous art, Paital discloses a substrate fiducial marker (Para 0066). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur’s device by having Pailtal’s disclosure in order to improve the alignment of different components of a semiconductor device.
With respect to claim 13, Alur discloses wherein the interconnect bridge is embedded within
the substrate (Fig. 1D), and a top surface of the interconnect bridge and a top surface of the substrate form a coplanar top surface (Fig. 1D).
With respect to claim 14, Alur discloses wherein all vertical connections in the coplanar top
surface include tin at an interface below the coplanar top surface (Col. 4; lines 10-15; Sn or NiSn bond layer).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Alur/Paital in view of Hwang (US 2019/0206796, hereinafter Hwang).
With respect to claim 11, Alur/Paital does not explicitly disclose wherein the bridge fiducial marker includes tin at an exposed surface.
In an analogous art, Hwang discloses wherein the bridge fiducial marker includes tin at an exposed surface (Para 0076). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur/Pailtal’s device by having Hwang’s disclosure in order to improve the alignment of different components of a semiconductor device by distinguishing from other components.
With respect to claim 12, Alur/Paital does not explicitly disclose wherein
the substrate fiducial marker includes tin at an exposed surface.
In an analogous art, Hwang discloses wherein the substrate fiducial marker includes tin at an exposed surface (Para 0076). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Alur/Pailtal’s device by having Hwang’s disclosure in order to improve the alignment of different components of a semiconductor device by distinguishing from other components.
Conclusion
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899