Prosecution Insights
Last updated: April 19, 2026
Application No. 18/089,491

LIQUID METAL WELLS FOR INTERCONNECT ARCHITECTURES

Non-Final OA §102§103
Filed
Dec 27, 2022
Examiner
WOLDEGEORGIS, ERMIAS T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
83%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
526 granted / 743 resolved
+2.8% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
49 currently pending
Career history
792
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
68.7%
+28.7% vs TC avg
§102
26.6%
-13.4% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 743 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 4, 5 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inagaki et al. (US 2005/0157478 A1, hereinafter “Inagaki”). In regards to claim 1, Inagaki discloses (See, for example, Fig. 7) a package substrate, comprising: a core (30); buildup layers (80A, 80B) over the core (30); a pad (“PAD”, see annotated Fig. 8 included below) on the buildup layers (80A, 80B); and a liquid metal well (71U) over the pad (“PAD”, See annotated Fig. 8 included below). In regards to claim 2, Inagaki discloses (See, for example, Fig. 7) a mold layer (70) over the buildup layers (80a, 80B), wherein the liquid metal well (71U) is provided through the mold layer (70). In regards to claim 4, Inagaki discloses (See, for example, Fig. 7) the liquid metal well (71U) includes sloped sidewalls. In regards to claim 5, Inagaki discloses (see, for example, Fig. 7) the core (30) comprises glass (See, for example, Par 6 in page 19, “As a core substrate … such a glass epoxy resin-impregnated…” ). In regards to claim 6, Inagaki discloses (See, for example, Fig. 7) a surface finish (See, for example, 72/74) over the pad (“PAD”, See, annotated Fig. 8 included below). Claims 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meyyappan et al. (US 2021/0392774 A1, hereinafter “Meyyappan”). In regards to claim 12, Meyyappan discloses (See, for example, Figs. 1A/1B) a computing system, comprising: a package substrate (101/110); a die (102) coupled to the package substrate (101/110); a well (116) in the package substrate (101/110), wherein the well (116) is at least partially filled by a liquid metal (113); and a component (121) coupled to the package substrate (101/110), wherein the component (121) includes a post (122) that is inserted into the well (116). In regards to claim 13, Meyyappan discloses (See, for example, Figs. 1A/1B) the component (121) is electrically coupled to the die (102) through the package substrate (101/110). 443 In regards to claim 14, Meyyappan discloses (See, for example, Figs. 1A/1B) the die is a processor (See, for example, Par [0067]), and wherein the component comprises co-packaged optics (See, for example, Pars [0064]- [0068]). In regards to claim 15, Meyyappan discloses (See, for example, Figs. 1A/1B) the liquid metal (113) comprises gallium and/or indium (See, for example, Par [0024]). In regards to claim 16, Meyyappan discloses (see, for example, Figs. 1A/1B) the component is a second die (See, for example, the socket substrate may be a board, See Par [0030]; See also, Pars [0064] and [0065]). In regards to claim 17, Meyyappan discloses the second die comprises a memory die ( “…components include … volatile memory (e.g. DRAM), non-volatile memory (e.g. ROM), flash memory…”, See Pars [0064] and [0065]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Inagaki in view of Ju et al. (US 2015/0146395 A1, hereinafter “Ju”). In regards to claim 7, Inagaki discloses all limitations of claim 1 above except that the liquid metal comprises gallium and/or indium. Ju while disclosing electric connectors with contact pad teaches (See, for example, Figs. 5) the liquid metal (31) comprises gallium and/or indium (See, for example, Par [0054]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Inagaki by Ju because the electrical connector is electrically connected with the circuit board by utilizing the low-melting point metal so as to reduce thickness of an electric connector in an effective manner, which is simple to manufacture and has low production cost. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Inagaki in view of Qian et al. (WO 2017111957 A1, however, its US equivalent US PG PUB has been used for the rejection below, 2020/0243448 A1, hereinafter “Qian”) In regards to claims 8 and 9, Inagaki discloses all limitations of claim 1 above except that a land side capacitor coupled to the buildup layers; and the land side capacitor is provided in a mold layer over the buildup layers. Qian while disclosing a semiconductor package teaches (See, for example, Fig. 2) a land side capacitor (226/228) coupled to the buildup layers (204/210/220); and the land side capacitor (226/228) is provided in a mold layer (242) over the buildup layers (204/210/220). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Inagaki by Qian because the package reduces stresses, imparts flame retardant properties, promotes adhesion and reduces moisture uptake in molding. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Inagaki in view of Meyyappan. In regards to claim 10, Inagaki discloses all limitations of claim 1 above except that a board coupled to the package substrate, wherein the board comprises a pin that is inserted into the liquid metal well. Meyyappan discloses (See, for example, Figs. 1A/1B) a board (121) coupled to the package substrate (101/110), wherein the board (121) comprises a pin (122) that is inserted into the liquid metal well (116). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Inagaki by Meyyappan because the liquid metal interconnect in the semiconductor device is simple to manufacture and cost effective. This would also improve the long-term reliability of the liquid metal. In regards to claim 11, Inagaki as modified above discloses (See, for example, Fig. 8, Meyyappan) the board is part of a computing system for a mobile device, a tablet, an automobile, a personal computer, or a server (See, for example, Pars [0064]-[0068]). PNG media_image1.png 720 1033 media_image1.png Greyscale Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 18 is allowed over the prior art of record. The following is an examiner’s statement of reasons for allowance: Qian discloses A computing system, comprising: a mold layer; a first die over the mold layer; a second die over the mold layer and adjacent to the first die; a bridge die in the mold layer, wherein the bridge die communicatively couples the first die to the second die However, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach wells into the mold layer, wherein the wells are at least partially filled with a liquid metal. Claims 19-20 are also allowed as being dependent of the allowed independent base claim. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 27, 2022
Application Filed
Aug 02, 2023
Response after Non-Final Action
Aug 07, 2023
Examiner Interview (Telephonic)
Aug 07, 2023
Examiner Interview Summary
Feb 17, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
83%
With Interview (+11.9%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 743 resolved cases by this examiner. Grant probability derived from career allow rate.

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