DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 07/23/2006 has been entered. Claims 1-3, 6-12, 21, 24 and 25 remain pending in the application. Claims 4-5 and 22-23 have been cancelled. Claims 13-20 have been withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Levesque JR. et al., (United States Patent Application Publication Number, US 2024/0351945 A1), hereinafter referenced as Levesque, in view of Marks et al., (United States Patent Number, US 4,798,959), hereinafter referenced as Marks, in view of Mukai et al., (United States Patent Application Publication Number, US 2023/0284393 A1), hereinafter referenced as Mukai.
Regarding claim 1, Levesque teaches a package substrate, comprising: a layer, wherein the layer is a dielectric material (Fig.2A, element #100 is glass, paragraph [0044], row 1), a via opening through a thickness of the layer (Fig.2A, elements #120 are vias); and a conductive via in the via opening (Fig.1, element #20), wherein the conductive via has a substantially uniform composition throughout a thickness of the conductive via (entire via is filled with same material, copper, paragraph [0054], rows 6-7), and wherein the conductive via directly contacts the layer (Fig.1, element #20 directly contacts element #15, element #15 is equivalent to element #112 of Fig.2A)
Levesque teaches the layer comprises glass (element #100 is glass, paragraph [0044], row 1), which comprises SiO2. Levesque does not teach the layer comprising oxygen ions bonded to silicon. Marks teaches oxygen ions at the surface of a glass layer bonded to silicon (column 9, rows 14-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Marks and disclose oxygen ions at the surface of a glass layer bonded to silicon. As disclosed by Marks, the ions are the results of dissociation of silanol groups that exist naturally on the surface of glass (column 9, rows 11-21).
Levesque teaches copper directly contacts the surface of the layer (surface of the via) which is made of glass. Levesque does not teach wherein the conductive via directly contacts the layer to provide copper ions coupled to the oxygen ions of the layer by ionic bonds. Marks teaches oxygen ions at the surface of a glass layer bonded to silicon (column 9, rows 14-21, and column 10, rows 5-6), and making the surface electronegative and capable of reacting with positive ions (column 9, rows 24-37), by exposing the negative free bond of oxygen (column 17, rows 34-39). Marks further teaches making ionic bonds between positive ions and the negative bonds of the substrate (free bonds of oxygen) (column 8, rows 22-26). While Marks only teaches tin or palladium positive ions, Mukai teaches making the surface of a dielectric layer electronegative and capable of reacting with positive ions (paragraph [0029], rows 1-9), of palladium, tin or copper (paragraph [0139], rows 5-6). Therefore, the combination of Marks and Mukai teaches copper ions coupled to the oxygen ions of the layer by ionic bonds. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Marks and Mukai and disclose copper ions coupled to the oxygen ions of the layer by ionic bonds. The ionic bonds are stronger than covalent bonds, and, as disclosed by Mukai, they allow achieving high adhesion between copper and the dielectric layer.
Regarding claim 2, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. Levesque further teaches the package substrate of claim 1, wherein the layer comprises glass (Fig.2A, element #100 is glass, paragraph [0044], rows 1).
Regarding claim 3, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. Levesque further teaches the package substrate of claim 1, wherein the conductive via comprises copper (paragraph [0054], rows 6-7).
Regarding claim 6, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. Levesque further teaches the package substrate of claim 1, further comprising: a pad over a top surface of the layer and connected to the conductive via (Fig.1, element #20 has a pad over the top surface of element #15, element #15 is equivalent to element #112 of Fig.2A).
Regarding claim 8, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. Levesque further teaches the package substrate of claim 6, wherein the pad directly contacts the layer (Fig.1, the pad directly contact element #15, element #15 is equivalent to element #112 of Fig.2A).
Regarding claim 10, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. Levesque further teaches the package substrate of claim 1, wherein the conductive via has an aspect ratio (height:width) that is approximately 5:1 or greater (height can be 75um, paragraph [0049], row 5, and width can by 15um, paragraph [0050], row 3).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Marks, Mukai and in view of Duckworth et al., (United States Patent Application Publication Number, US 2013/0069680 A1) hereinafter referenced as Duckworth.
Regarding claim 7, the combination of Levesque, Marks and Mukai teaches the package substrate of claims 1 and 6 as set forth in the obviousness rejection. The combination of Levesque, Marks and Mukai does not teach the package substrate of claim 6, wherein a surface of the pad has an average surface roughness (Ra) that is less than approximately 50nm. Duckworth teaches wherein a surface of the pad has an average surface roughness that is less than 250nm (paragraph [0060], rows 8-9). The claimed range, of less than 50nm, overlaps or lies inside the range disclosed by Duckworth and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Duckworth and disclose wherein a surface of the pad has an average surface roughness that is less than approximately 50nm. Smooth contact pads can help control solder flow when solder is used for bonding, and are ideal for low temperature fusion bonding, where smooth surfaces are necessary to prevent the formation of voids.
Claims 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Marks, Mukai and in view of Sundaram et al., (United States Patent Application Publication Number, US 2016/0111380 A1) hereinafter referenced as Sundaram.
Regarding claim 9, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. The combination of Levesque, Marks and Mukai does not teach the package substrate of claim 1, wherein the layer is a core of a package substrate. Sundaram teaches wherein the layer is a core of a package substrate (Fig.1, element #108 is a core of a package substrate). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sundaram and disclose the layer is a core of a package substrate. As disclosed by Sundaram, using glass as the core of the substrate is cost effective when compared to silicon substrates, and can achieve higher I/O contact pitches when compared to organic substrates (paragraph [0058] and [0059]).
Regarding claim 12, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. The combination of Levesque, Marks and Mukai does not teach the package substrate of claim 1, wherein the package substrate is a core for an electronic package, and wherein the electronic package is coupled to a board. Sundaram teaches wherein the package substrate is a core for an electronic package, and wherein the electronic package is coupled to a board (Fig.1, shows the package and the substrate is coupled to board element #102). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sundaram and disclose wherein the package substrate is a core for an electronic package, and wherein the electronic package is coupled to a board. The board can provide power and signal to IC devices coupled to the package substrate.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Marks, Mukai and in view of Tarng et al., (United States Patent Application Publication Number, US 2013/0122216 A1) hereinafter referenced as Tarng.
Regarding claim 11, the combination of Levesque, Marks and Mukai teaches the package substrate of claim 1 as set forth in the obviousness rejection. The combination of Levesque, Marks, and Mukai does not teach the package substrate of claim 1, wherein there is no seed layer between the conductive via and the layer. Tarng teaches wherein there is no seed layer between the conductive via and the layer (Fig.2C and 2D the conductive via, element #26 is deposited in one step in the via opening, element #22, paragraph [0011], rows 8-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tarng and disclose there is no seed layer between the conductive via and the layer. As disclosed by Tarng, this allows the conductive material in the via to be deposited in a single process step, together with other circuit metal traces, which reduces the number of processing steps and cost.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sundaram in view of Marks and Mukai.
Regarding claim 21, Sundaram teaches an electronic system, comprising: a board (Fig. 1, element #102); a package substrate coupled to the board (Fig.1, substrate between element #102 and element #106), wherein the package substrate comprises: a core, wherein the core comprises glass (Fig.1, element #108).
Sundaram teaches the layer comprises glass which comprises SiO2. Sundaram does not teach the layer comprising oxygen ions bonded to silicon. Marks teaches oxygen ions at the surface of a glass layer bonded to silicon (column 9, rows 14-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Marks and disclose oxygen ions at the surface of a glass layer bonded to silicon. As disclosed by Marks, the ions are the results of dissociation of silanol groups that exist naturally on the surface of glass (column 9, rows 11-21).
Sundaram further teaches a through glass via (TGV) through the core (Fig.1, element #104), wherein the TGV directly contacts the core without an intervening seed layer (Fig.8, paragraph [0076], rows 4-10); buildup layers over the core (Fig.1, layers above the glass core); and a die coupled to the package substrate (Fig.1, element #106).
Sundaram teaches copper directly contacts the surface of the layer (surface of the via, Fig.1) which is made of glass. Sundaram does not teach wherein the conductive via directly contacts the layer to provide copper ions coupled to the oxygen ions of the glass by ionic bonds. Marks teaches oxygen ions at the surface of a glass layer bonded to silicon (column 9, rows 14-21, and column 10, rows 5-6), and making the surface electronegative and capable of reacting with positive ions (column 9, rows 24-37), by exposing the negative free bond of oxygen (column 17, rows 34-39). Marks further teaches making ionic bonds between positive ions and the negative bonds of the substrate (free bonds of oxygen) (column 8, rows 22-26). While Marks only teaches tin or palladium positive ions, Mukai teaches making the surface of a dielectric layer electronegative and capable of reacting with positive ions (paragraph [0029], rows 1-9), of palladium, tin or copper (paragraph [0139], rows 5-6). Therefore, the combination of Marks and Mukai teaches copper ions coupled to the oxygen ions of the layer by ionic bonds. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Marks and Mukai and disclose copper ions coupled to the oxygen ions of the layer by ionic bonds. The ionic bonds are stronger than covalent bonds, and, as disclosed by Mukai, they allow achieving high adhesion between copper and the dielectric layer.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Sundaram, in view of Marks, Mukai and in view of Duckworth.
Regarding claim 24, the combination of Sundaram, Marks, and Mukai teaches the electronic system of claim 21 as set forth in the obviousness rejection. Sundaram further teaches the electronic system of claim 21, further comprising: a pad over the TGV (Fig.1, the vias have top and bottom pads). The combination of Sundaram, Marks, and Mukai does not teach wherein the pad has an average surface roughness (Ra) of less than approximately 50nm.
Duckworth teaches wherein a surface of the pad has an average surface roughness that is less than 250nm (paragraph [0060], rows 8-9). The claimed range of less than 50nm overlaps or lies inside the range disclosed by Duckworth and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Duckworth and disclose wherein a surface of the pad has an average surface roughness that is less than approximately 50nm. Smooth contact pads can help control solder flow when solder is used for bonding, and are ideal for low temperature fusion bonding, where smooth surfaces are necessary to avoid the formation of voids.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Sundaram, in view of Marks, Mukai and in view of Levesque.
Regarding claim 25, the combination of Sundaram, Marks, and Mukai teaches the electronic system of claim 21 as set forth in the obviousness rejection. The combination of Sundaram, Marks, and Mukai does not teach the electronic system of claim 21, wherein the TGV has an aspect ratio (height:width) that is approximately 5:1 or greater. Sundaram teaches the glass core has a thickness between 30um and 500um (paragraph [0005], rows 6-8). Levesque teaches wherein the conductive via has an aspect ratio (height:width) that is approximately 5:1 or greater (via height is equal to the substrate thickness, which can be 75um or greater, paragraph [0049], row 5, and width can by 15um, paragraph [0050], row 3). The claimed range of approximately 5:1 or greater, overlaps or lies inside the range disclosed by Levesque, and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Levesque and disclose wherein the TGV has an aspect ratio (height:width) that is approximately 5:1 or greater. The substrate thickness is determined by mechanical constraints, and making vias with small diameter and high aspect ratio reduces the space occupied by the vias, therefore allowing for a smaller package footprint.
Response to Arguments
Applicants’ arguments filed on 07/23/2026 have been fully considered but they
are not persuasive. Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
