DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-12 and 21-25, drawn to an electronic system comprising a substrate with vias and the substrate with vias, in the reply filed on 03/09/2026, is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 8 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Levesque JR. et al., (United States Patent Application Publication Number, US 2024/0351945 A1), hereinafter referenced as Levesque.
Regarding claim 1, Levesque teaches a package substrate, comprising: a layer, wherein the layer is a dielectric material (Fig.2A, element #100 is glass, paragraph [0044], rows 1); a via opening through a thickness of the layer (Fig.2A, elements #120 are vias); and a conductive via in the via opening (Fig.1, element #20), wherein the conductive via has a substantially uniform composition throughout a thickness of the conductive via (entire via is filled with same material, copper, paragraph [0054], rows 6-7), and wherein the conductive via directly contacts the layer (Fig.1, element #20 directly contacts element #15, element #15 is equivalent to element #112 of Fig.2A).
Regarding claim 2, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque further teaches the package substrate of claim 1, wherein the layer comprises glass (Fig.2A, element #100 is glass, paragraph [0044], rows 1).
Regarding claim 3, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque further teaches the package substrate of claim 1, wherein the conductive via comprises copper (paragraph [0054], rows 6-7).
Regarding claim 6, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque further teaches the package substrate of claim 1, further comprising: a pad over a top surface of the layer and connected to the conductive via (Fig.1, element #20 has a pad over the top surface of element #15, element #15 is equivalent to element #112 of Fig.2A).
Regarding claim 8, Levesque teaches the package substrate of claims 1 and 6 as set forth in the anticipation rejection. Levesque further teaches the package substrate of claim 6, wherein the pad directly contacts the layer (Fig.1, the pad directly contact element #15, element #15 is equivalent to element #112 of Fig.2A).
Regarding claim 10, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque further teaches the package substrate of claim 1, wherein the conductive via has an aspect ratio (height:width) that is approximately 5:1 or greater ( height can be 75um, paragraph [0049], row 5, and width can by 15um, paragraph [0050], row 3).
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sundaram et al., (United States Patent Application Publication Number, US 2016/0111380 A1) hereinafter referenced as Sundaram.
Regarding claim 21, Sundaram teaches an electronic system, comprising: a board (Fig. 1, element #102); a package substrate coupled to the board (Fig.1, substrate between element #102 and element #106), wherein the package substrate comprises: a core, wherein the core comprises glass (Fig.1, element #108); a through glass via (TGV) through the core (Fig.1, element #104), wherein the TGV directly contacts the core without an intervening seed layer (Fig.8, paragraph [0076], rows 4-10); and buildup layers over the core (Fig.1, layers above the glass core); and a die coupled to the package substrate (Fig.1, element #106).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Marks et al., (United States Patent Number, US 4,798,959) hereinafter referenced as Marks, in view of Mukai et al., (United States Patent Application Publication Number, US 2023/0284393 A1) hereinafter referenced as Mukai, and in view of Yagyu et al., (United States Patent Application Publication Number, US 2018/0082977 A1) hereinafter referenced as Yagyu.
Regarding claim 4, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque does not teach the package substrate of claim 1, wherein a bond between the conductive via and the layer is an ionic bond. Marks teaches a process of changing the surface of a glass so that hydroxyl groups are formed at the surface, and the surface becomes electronegative and capable of reacting with positive ions such as copper ions, forming ionic bonds (column 9, rows 24-37, and column 10, rows 21-29). Furthermore, Mukai teaches the formation of hydroxyl groups on the surface of a via formed in a dielectric layer and the deposition of a conductive via inside the via opening (Fig.1, paragraph [0029], rows 1-9). Yagyu also teaches forming ionic bond between copper and hydroxyl groups (Fig. 8C and paragraph [0060], rows 6-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Marks, Mukai and Yagyu and disclose wherein a bond between the conductive via and the layer is an ionic bond. Ionic bonds are strong and, as disclosed by Mukai, this allows achieving high adhesion between the conductive via and the layer.
Regarding claim 5, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection, and the combination of Levesque, Marks, Mukai and Yagyu teaches the package substrate of claim 4 as set forth in the obviousness rejection. Levesque does not teach the package substrate of claim 4, wherein ions of the conductive via are bonded to oxygen of the layer. Yagyu further teaches wherein metal ions are bonded to oxygen atoms of hydroxyl group (Fig. 8C, Cu ions bonded to oxygen of the hydroxyl group, paragraph [0060], rows 6-10) and Marks teaches oxygen atoms of hydroxyl group are at the surface of the dielectric (column 9, rows 35-36). Therefore, metal atoms can bond to the oxygen atoms at the surface of the layer. We note the oxygen atoms at the surface of the layer cannot be differentiated from oxygen atoms of the layer.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Duckworth et al., (United States Patent Application Publication Number, US 2013/0069680 A1) hereinafter referenced as Duckworth.
Regarding claim 7, Levesque teaches the package substrate of claims 1 and 6 as set forth in the anticipation rejection. Levesque does not teach the package substrate of claim 6, wherein a surface of the pad has an average surface roughness (Ra) that is less than approximately 50nm. Duckworth teaches wherein a surface of the pad has an average surface roughness that is less than 250nm (paragraph [0060], rows 8-9). The claimed range of less than 50nm overlaps or lies inside the range disclosed by Duckworth and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Duckworth and disclose wherein a surface of the pad has an average surface roughness that is less than 250nm. Smooth contact pads can help control solder flow when solder is used for bonding, and are ideal for low temperature fusion bonding, where smooth surfaces are necessary.
Claims 9 and 12 is rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Sundaram.
Regarding claim 9, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque does not teach the package substrate of claim 1, wherein the layer is a core of a package substrate. Sundaram teaches wherein the layer is a core of a package substrate (Fig.1, element #108 is a core of a package substrate). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sundaram and disclose the layer is a core of a package substrate. As disclosed by Sundaram, using glass as the core of the substrate is cost effective when compared to silicon substrates, and can achieve higher I/O contact pitches when compared to organic substrates (paragraph [0058] and [0059])
Regarding claim 12, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque does not teach the package substrate of claim 1, wherein the package substrate is a core for an electronic package, and wherein the electronic package is coupled to a board. Sundaram teaches wherein the package substrate is a core for an electronic package, and wherein the electronic package is coupled to a board (Fig.1, shows the package and the substrate is coupled to board element #102). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Sundaram and disclose wherein the package substrate is a core for an electronic package, and wherein the electronic package is coupled to a board. The board can provide power and signal to IC devices coupled to the package substrate.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Levesque, in view of Tarng et al., (United States Patent Application Publication Number, US 2013/0122216 A1) hereinafter referenced as Tarng.
Regarding claim 11, Levesque teaches the package substrate of claim 1 as set forth in the anticipation rejection. Levesque does not teach the package substrate of claim 1, wherein there is no seed layer between the conductive via and the layer. Tarng teaches wherein there is no seed layer between the conductive via and the layer (Fig.2C and 2D the conductive via, element #26 is deposited in one step in the via opening, element #22, paragraph [0011], rows 8-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tarng and disclose there is no seed layer between the conductive via and the layer. As disclosed by Tarng, this allows the conductive material in the via to be deposited in a single process step, together with other metal traces, which reduces the number of processing steps and cost.
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Sundaram, in view Marks, Mukai and Yagyu.
Regarding claim 22, Sundaram teaches the electronic system of claim 21 as set forth in the anticipation rejection. Sundaram does not teach the electronic system of claim 21, wherein the TGV is ionically bonded to the core. Marks teaches a process of changing the surface of a glass so that hydroxyl groups are formed at the surface, and the surface becomes electronegative and capable of reacting with positive ions such as copper ions, forming ionic bonds (column 9, rows 24-37, and column 10, rows 21-29). Furthermore, Mukai teaches the formation of hydroxyl groups on the surface of a via formed in a dielectric layer and the deposition of a conductive via inside the via opening (Fig.3, paragraph [0029], rows 1-9). Yagyu teaches forming ionic bonds between copper and hydroxyl groups (Fig.8C and paragraph [0060], rows 6-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Marks, Mukai and Yagyu and disclose wherein a bond between the conductive via and the layer is an ionic bond. Ionic bonds are strong and, as disclosed by Mukai, this allows achieving high adhesion between the conductive via and the layer (paragraph [0016]).
Regarding claim 23, Sundaram teaches the electronic system of claim 21 as set forth in the anticipation rejection, and the combination of Sundaram, Marks, Mukai and Yagyu teaches the electronic system of claim 22 as set forth in the obviousness rejection. Sundaram does not teach the electronic system of claim 22, wherein ions of the TGV are bonded to oxygen of the core. Yagyu further teaches wherein metal ions are bonded to oxygen of hydroxyl group (Fig. 8C, Cu ions bonded to oxygen of the hydroxyl group, paragraph [0060], rows 6-10) and Marks teaches the oxygen atoms are at the surface of the dielectric (column 9, rows 35-36). Therefore, metal atoms can bond to the oxygen atoms at the surface of the layer. We note that the oxygen atoms at the surface of the core cannot be differentiated from oxygen atoms of the core.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Sundaram, in view of Duckworth.
Regarding claim 24, Sundaram teaches the electronic system of claim 21 as set forth in the anticipation rejection. Sundaram further teaches the electronic system of claim 21, further comprising: a pad over the TGV (Fig.1, the vias have to and bottom pads). Sundaram does not teach wherein the pad has an average surface roughness (Ra) of less than approximately 50nm.
Duckworth teaches wherein a surface of the pad has an average surface roughness that is less than 250nm (paragraph [0060], rows 8-9). The claimed range of less than 50nm overlaps or lies inside the range disclosed by Duckworth and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Duckworth and disclose wherein a surface of the pad has an average surface roughness that is less than 250nm. Smooth contact pads can help control solder flow when solder is used for bonding, and are ideal for low temperature fusion bonding, where smooth surfaces are necessary.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Sundaram, in view of Levesque.
Regarding claim 25, Sundaram teaches the electronic system of claim 21 as set forth in the anticipation rejection. Sundaram does not teach the electronic system of claim 21, wherein the TGV has an aspect ratio (height:width) that is approximately 5:1 or greater. Sundaram teaches the glass core has a thickness between 30um and 500um (paragraph [0005], rows 6-8). Levesque teaches wherein the conductive via has an aspect ratio (height:width) that is approximately 5:1 or greater (via height is equal to the substrate thickness, which can be 75um or greater, paragraph [0049], row 5, and width can by 15um, paragraph [0050], row 3). The claimed range of approximately 5:1 or greater, overlaps or lies inside the range disclosed by Levesque, and therefore a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Levesque and disclose wherein the TGV has an aspect ratio (height:width) that is approximately 5:1 or greater. The substrate thickness is determined by mechanical constraints, and making vias with small diameter, high aspect ratio, reduces the space occupied by the vias, therefore allowing for a smaller footprint.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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