DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10 & 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over SUGISAKI (US PUB. 2020/0098776) in view of Toma et al. (US Pub. 2024/0036278) and HARADA et al. (US Pub. 2024/0194250).
Regarding claim 1, SUGISAKI teaches a three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising an array of first type memory cells 100 (see Fig. 17 below);
a second semiconductor structure comprising an array of memory cells (Fig. 17 below);
a third semiconductor structure comprising a first peripheral circuit 200 (see Fig. 17 below); and
a fourth semiconductor structure comprising a second peripheral circuit 200 (see Fig. 17 below and note the annotations);
wherein the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another (Fig. 17).
PNG
media_image1.png
930
892
media_image1.png
Greyscale
SUGISAKI is silent on wherein the array of memory cells in the second semiconductor structure is an array of second type memory cells different from the first type memory cells, wherein the second type memory cells are multi-gate dynamic flash memory (DFM) cells.
However, Toma teaches a 3D memory device, wherein an array of memory cells in the second semiconductor structure (any of 104a-104g) is an array of second type memory cells different from a first type memory cells (DRAM in the base die 102), wherein the second type memory cells are dynamic flash memory (DFM) cells (Para [0023] and Fig. 1). One of the ordinary skill in the art being one of the ordinary creativity would recognize the advantages of DFM cells offering higher density, capacity and speed for the semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of SUGISAKI with the DFM cells, as taught by Toma, so as to obtain an improved semiconductor device with higher density, speed and capacity.
Both SUGISAKI and Toma are silent on wherein the dynamic flash memory (DFM) cells are multi-gate. However, HARADA teaches a dynamic flash memory (DFM) comprising a plurality of gates (21aa, 22aa, 22ba & 21ba, see Fig. 1KB and Para [0097]). Multi-gate DFM cells provide ultra-high density, fast block refreshing and low leakage current. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of SUGISAKI and Toma with the multi-gate DFM cells, as taught by HARADA, so as to obtain an improved semiconductor device with ultra-high density, higher speed and low leakage current capabilities.
Regarding claim 2, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 1, wherein: the first semiconductor structure further comprises a first semiconductor layer (note semiconductor layer 902 in TOMA’s Fig. 14); the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer (see SUGISAKI’s Fig. 17 above); the second semiconductor structure further comprises a second semiconductor layer; and the array of second type memory cells (TOMA’s Fig. 1 & Para [0023]) is formed on the second semiconductor layer (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Regarding claim 3, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 2, wherein: the third semiconductor structure further comprises a third semiconductor layer 30; the first peripheral circuit 200 comprises a plurality of first type transistors having a first operating voltage on the third semiconductor layer; the fourth semiconductor structure further comprises a fourth semiconductor layer 30 (see Fig. 15 and Fig. 17 above); and the second peripheral circuit 200 comprises a plurality of third type transistors having a third operating voltage on the fourth semiconductor layer, wherein the third operating voltage can be lower than the first operating voltage (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Furthermore, the limitation “wherein the third operating voltage can be lower than the first operating voltage”, is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 4, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 3, wherein: the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage; and the third and fourth semiconductor layers have different thicknesses (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Regarding claim 5, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 4, wherein: the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells; the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the first peripheral circuit; and the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the second peripheral circuit (note the various interconnect layers making connections to the memory cells and the peripheral circuits in SUGISAKI’s Fig. 17 & TOMA’s Fig. 1).
Regarding claim 21, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 1, wherein each multi-gate DFM cell comprises a word line and a plurality of plate lines (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Regarding claim 10, SUGISAKI teaches a system (Fig. 1), comprising:
a memory device 10 configured to store data, and comprising:
a first semiconductor structure comprising an array of first type memory cells 100 (see Fig. 17 above),
a second semiconductor structure comprising an array of second type memory cells (Fig. 17 above);
a third semiconductor structure comprising a first peripheral circuit 200 (see Fig. 17 above), and
a fourth semiconductor structure comprising a second peripheral circuit 200 (see Fig. 17 above and note the annotations);
wherein the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another (Fig. 17); and
a memory controller 20 coupled to the memory device 10 and configured to control the array of first type memory cells and the array of second type memory cells through the first peripheral circuit and the second peripheral circuit (Fig. 1 & Fig. 17).
SUGISAKI is silent on wherein the array of memory cells in the second semiconductor structure is an array of second type memory cells different from the first type memory cells, wherein the second type memory cells are multi-gate dynamic flash memory (DFM) cells.
However, Toma teaches a 3D memory device, wherein an array of memory cells in the second semiconductor structure (any of 104a-104g) is an array of second type memory cells different from a first type memory cells (e.g. DRAM in the base die 102), wherein the second type memory cells are dynamic flash memory (DFM) cells (Para [0023] and Fig. 1). One of the ordinary skill in the art being one of the ordinary creativity would recognize the advantages of DFM cells offering higher density, capacity and speed for the semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of SUGISAKI with the DFM cells, as taught by Toma, so as to obtain an improved semiconductor device with higher density, speed and capacity.
Both SUGISAKI and Toma are silent on wherein the dynamic flash memory (DFM) cells are multi-gate. However, HARADA teaches a dynamic flash memory (DFM) cell comprising a plurality of gates (21aa, 22aa, 22ba & 21ba, see Fig. 1KB and Para [0097]). Multi-gate DFM cells provide ultra-high density, fast block refreshing and low leakage current. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of SUGISAKI and Toma with the multi-gate DFM cells, as taught by HARADA, so as to obtain an improved semiconductor device with ultra-high density, higher speed and low leakage current capabilities.
Regarding claim 22, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 10, wherein: the first semiconductor structure further comprises a first semiconductor layer (note semiconductor layer 902 in TOMA’s Fig. 14); the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer (see SUGISAKI’s Fig. 17 above); the second semiconductor structure further comprises a second semiconductor layer; and the array of second type cells (TOMA’s Fig. 1 & Para [0023]) is formed on the second semiconductor layer (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Regarding claim 23, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 22, wherein: the third semiconductor structure further comprises a third semiconductor layer 30; the first peripheral circuit 200 comprises a plurality of first type transistors having a first operating voltage on the third semiconductor layer; the fourth semiconductor structure further comprises a fourth semiconductor layer 30 (see Fig. 15 and Fig. 17 above); and the second peripheral circuit 200 comprises a plurality of third type transistors having a third operating voltage on the fourth semiconductor layer, wherein the third operating voltage can be lower than the first operating voltage (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Furthermore, the limitation “wherein the third operating voltage can be lower than the first operating voltage”, is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 24, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 23, wherein: the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage; and the third and fourth semiconductor layers have different thicknesses (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Regarding claim 25, the combination of SUGISAKI, Toma and HARADA teaches the 3D memory device of claim 24, wherein: the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells; the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the first peripheral circuit; and the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the second peripheral circuit (note the various interconnect layers making connections to the memory cells and the peripheral circuits in SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 30, the combination of SUGISAKI, Toma and HARADA the 3D memory device of claim 22, wherein each multi-gate DFM memory cell comprises a word line and a plurality of plate lines (SUGISAKI’s Fig. 17, TOMA’s Fig. 1 and HARADA’s Fig. 1KB).
Allowable Subject Matter
Claims 6-9 & 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 &10 have been considered but are moot in light of new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-2829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818
Prosecution Insights