DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 21, 10 and 22-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 & 10 recites the limitation “an array of first type memory cells” in lines 2 and line 3 respectively. Said limitation raises ambiguity as it implies that there is “a second type memory cells” that has not been recited in the claim. Correction/Clarification is required
Claims 1 & 10 further recite “an array of multi-gate dynamic flash memory (DFM) memory cells”. The limitation raises ambiguity as the term memory appears to be redundant and/or whether DFM cells and within memory cells. Correction/clarification is required.
Claim 2 recites the limitation “the array of multi-gate DFM cells”, which lacks sufficient antecedent basis. Correction is required.
Claims 2-10 , 21 and 22-30 are rejected for being dependent on claims 1 & 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10 & 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over SUGISAKI (US PUB. 2020/0098776) in view of Toma et al. (US Pub. 2024/0036278).
Regarding claim 1, SUGISAKI teaches a three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising an array of first type memory cells 100 (see Fig. 17 below);
a second semiconductor structure comprising an array of memory cells (Fig. 17 below);
a third semiconductor structure comprising a first peripheral circuit 200 (see Fig. 17 below); and
a fourth semiconductor structure comprising a second peripheral circuit 200 (see Fig. 17 below and note the annotations);
wherein the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another (Fig. 17).
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SUGISAKI is silent on wherein the array of memory cells in the second semiconductor structure is an array of multi-gate dynamic flash memory (DFM) memory cells different from the array of first type memory cells. However, Toma teaches a 3D memory device, wherein an array of multi-gate dynamic flash memory (DFM) memory cells in a second semiconductor structure (any of 104a-104g) is different from an array of first type memory cell (e.g. DRAM) in a first semiconductor structure (any of 104a-104g, Fig. 1 and Para [0023]). One of the ordinary skill in the art being one of the ordinary creativity would recognize the advantages of DFM cells offering higher density, capacity and speed for the semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of SUGISAKI with the DFM cells, as taught by Toma, so as to obtain an improved semiconductor device with higher density, speed and capacity.
Regarding claim 2, the combination of SUGISAKI and Toma teaches the 3D memory device of claim 1, wherein: the first semiconductor structure further comprises a first semiconductor layer (note semiconductor layer 902 in TOMA’s Fig. 14); the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer (see SUGISAKI’s Fig. 17 above); the second semiconductor structure further comprises a second semiconductor layer; and the array of multi-gate DFM cells (TOMA’s Fig. 1 & Para [0023]) are formed on the second semiconductor layer (SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 3, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 2, wherein: the third semiconductor structure further comprises a third semiconductor layer 30; the first peripheral circuit 200 comprises a plurality of first type transistors having a first operating voltage on the third semiconductor layer; the fourth semiconductor structure further comprises a fourth semiconductor layer 30 (see Fig. 15 and Fig. 17 above); and the second peripheral circuit 200 comprises a plurality of third type transistors having a third operating voltage on the fourth semiconductor layer, wherein the third operating voltage can be lower than the first operating voltage (SUGISAKI’s Fig. 15 & 17 and TOMA’s Fig. 1).
Furthermore, the limitation “wherein the third operating voltage can be lower than the first operating voltage”, is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 4, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 3, wherein: the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage; and the third and fourth semiconductor layers have different thicknesses (SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 5, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 4, wherein: the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells; the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the first peripheral circuit; and the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the second peripheral circuit (note the various interconnect layers making connections to the memory cells and the peripheral circuits in SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 21, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 1, wherein each multi-gate DFM memory cell comprises a word line and a plurality of plate lines (SUGISAKI’s Fig. 2 and TOMA’s Fig. 1).
Regarding claim 10, SUGISAKI teaches a system (Fig. 1), comprising:
a memory device 10 configured to store data, and comprising:
a first semiconductor structure comprising an array of first type memory cells 100 (see Fig. 17 above),
a second semiconductor structure comprising an array of memory cells (Fig. 17 above);
a third semiconductor structure comprising a first peripheral circuit 200 (see Fig. 17 above), and
a fourth semiconductor structure comprising a second peripheral circuit 200 (see Fig. 17 above and note the annotations);
wherein the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another (Fig. 17); and
a memory controller 20 coupled to the memory device 10 and configured to control the array of first type memory cells and the array of second type memory cells through the first peripheral circuit and the second peripheral circuit (Fig. 1 & Fig. 17).
SUGISAKI is silent on wherein the array of memory cells in the second semiconductor structure is an array of multi-gate dynamic flash memory (DFM) memory cells different from the array of first type memory cells. However, Toma teaches a 3D memory device, wherein an array of multi-gate dynamic flash memory (DFM) memory cells in a second semiconductor structure (any of 104a-104g) is different from an array of first type memory cell (e.g. DRAM) in a first semiconductor structure (any of 104a-104g, Fig. 1 and Para [0023]). One of the ordinary skill in the art being one of the ordinary creativity would recognize the advantages of DFM cells offering higher density, capacity and speed for the semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of SUGISAKI with the DFM cells, as taught by Toma, so as to obtain an improved semiconductor device with higher density, speed and capacity.
Regarding claim 22, the combination of SUGISAKI and Toma teaches the 3D memory device of claim 10, wherein: the first semiconductor structure further comprises a first semiconductor layer (note semiconductor layer 902 in TOMA’s Fig. 14); the array of first type memory cells comprises an array of NAND memory strings formed on the first semiconductor layer (see SUGISAKI’s Fig. 17 above); the second semiconductor structure further comprises a second semiconductor layer; and the array of multi-gate DFM cells (TOMA’s Fig. 1 & Para [0023]) are formed on the second semiconductor layer (SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 23, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 22, wherein: the third semiconductor structure further comprises a third semiconductor layer 30; the first peripheral circuit 200 comprises a plurality of first type transistors having a first operating voltage on the third semiconductor layer; the fourth semiconductor structure further comprises a fourth semiconductor layer 30 (see Fig. 15 and Fig. 17 above); and the second peripheral circuit 200 comprises a plurality of third type transistors having a third operating voltage on the fourth semiconductor layer, wherein the third operating voltage can be lower than the first operating voltage (SUGISAKI’s Fig. 15 & 17 and TOMA’s Fig. 1).
Furthermore, the limitation “wherein the third operating voltage can be lower than the first operating voltage”, is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 24, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 23, wherein: the first peripheral circuit or the second peripheral circuit comprises a plurality of second type transistors having a second operating voltage lower than the first operating voltage and higher than the third operating voltage; and the third and fourth semiconductor layers have different thicknesses (SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 25, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 24, wherein: the first semiconductor structure further comprises a first interconnect layer comprising a first interconnect coupled to the array of NAND memory strings; the second semiconductor structure further comprises a second interconnect layer comprising a second interconnect coupled to the array of multi-gate DFM cells; the third semiconductor structure further comprises a third interconnect layer comprising a third interconnect coupled to the first peripheral circuit; and the fourth semiconductor structure further comprises a fourth interconnect layer comprising a fourth interconnect coupled to the second peripheral circuit (note the various interconnect layers making connections to the memory cells and the peripheral circuits in SUGISAKI’s Fig. 17 and TOMA’s Fig. 1).
Regarding claim 30, the combination of SUGISAKI and TOMA teaches the 3D memory device of claim 22, wherein each multi-gate DFM memory cell comprises a word line and a plurality of plate lines (SUGISAKI’s Fig. 2 and TOMA’s Fig. 1).
Allowable Subject Matter
Claims 6-9 & 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 &10 have been considered but are moot in light of new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818