DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/089,546 filed on 12/27/2022. Claims 1-20 are pending in the office action.
Claim Objections
Claims 7 and 16 are objected to because of the following informalities:
As per claim 7: changes it dependency to claim 5 (Note: otherwise, potentially violated 35 U.S.C 112 second paragraph)
As per claim 16: changes it dependency to claim 14 (similar as per claim 7 above).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dokken et al., (U.S. Pat. 7,568,139) in view of Guo et al, (U.S. Pat. 8,316,265).
As per claims 1, 10, and 19: Dokken teaches a device, the device comprising:
processing circuitry coupled to storage (computer readable media) (‘139, col. 6, ll. 7-8), the processing circuitry configured to:
perform a functional test on a processor (CPU) cell in a chain (‘139, col. 3, ll. 7-17, functional testers, col. 6, ll. 8-12, a processor (CPU) perform test for scan cell in a chain);
propagate data through a combinatoric logic (‘139, fig. 2-4 and fig. 6, combination logic (i.e., cloud representation) as inverter represented a (first) combination logic, col. 1, line 65 – col. 2, line 1, col. 4, ll. 35-38, combination logic);
capture results in sequential flip-flops associated with scan (‘139, col. 2, ll. 1-4, the scan chain is once more applied and the result data as captured at scan cell 1, fig. 2-4 and fig. 6, the output Q of sequential flip-flop 202);
utilize the results in a next combinatoric logic (‘139, fig. 2-4 and fig. 6, as taking AND gate 220 as (next) combination logic, the result of the sequential flip-flop 202 having a path input AND gate 220 and another path feed into Mux and sequential flip-flop 204); and
utilize shifted-out data to isolate a first broken cell based on the functional test (‘139, fig. 4 and fig. 6, col. 4, ll. 28-60).
Dokken teaches a processor (CPU), but does not teach a plurality of central processing units (CPU).
Guo teaches different techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution that are able to isolate a scan chain defect to a single scan cell (‘265, the abstract). Guo also teaches a computing environment having multiple computers (processors, CPUs) for performing scan chain diagnostic or test pattern generation (‘265, fig. 30, computers (CPUs) 3002 and also see fig. 29 and fig. 31-33).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Guo’s computing environment into the Dokken’s computing system to modify a computing system into a multi-processing system with multiple processing unit to increase processing power for performing scan chain diagnostic or test pattern generation (‘265, col. 8, ll. 4-11).
As per claims 2, 11, and 20: Dokken and Guo teaches wherein the shifted-out data is a scan dump (‘139, fig. 2, col. 1, ll. 55-63 and col. 4, ll. 44-53).
As per claims 3 and 12: Dokken and Guo teaches wherein the shifted-out data is determined by shifting-out of sequential flip-flops data by serial flip-flops data (‘139, fig. 2-4 and fig, 6 and ‘256, fig. 1-2).
As per claims 4 and 13: Dokken and Guo teaches wherein the serial flip-flops are connected to the chain (‘265, fig. 9, scan chain 1-N).
As per claims 5 and 14: Dokken and Guo teaches wherein the processing circuitry is further configured to hold execution of the functional test for a predetermined time period (‘139, col. 2, ll. 46-22, scan enable (SE), the functional logic is removed (i.e., execution of the test to be hold)).
As per claims 6 and 15: Dokken and Guo teaches wherein the predetermined time period is a number of CPU cycles (‘139, col. 2, ll. 50-53, number of clock cycle n is equal to number of scan cells in the chain, col. 4, ll. 20-26, tester cycle count).
As per claims 7 and 16: Dokken and Guo teaches wherein the processing circuitry is further configured to resume the execution of the functional test after the data has been shifted-out (‘139, col. 2, ll. 50-53 and col. 4, ll. 33-38, resuming when SE is toggling).
As per claims 8 and 17: Dokken and Guo teaches wherein the processing circuitry is further configured to repeat holding the execution of the functional test and resuming the execution of the functional test until completion of the functional (‘139, col. 2, ll. 46-53, scan enable (SE), the functional logic is removed (i.e., execution of the test to be hold) and col. 2, ll. 50-53 and col. 4, ll. 33-38, resuming when SE is toggling).
As per claims 9 and 18: Dokken and Guo teaches wherein the shifted-out data is accumulated data after the completion of the functional test (‘139, the abstract, col. 3, ll. 32-38 and col. 6, ll. 16-30).
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851