DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending. Claims 1, 12, and 20 are amended. Claims 17-19 are cancelled.
Response to Arguments/Amendment
Applicant’s arguments, see pages 10-16, filed 10/17/2025, with respect to the rejections of amended claims 1 and 20 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Lue2 (KR 2015/0134260, translation provided for citation).
Specifically, the amendment of the claim limitation “in the height direction, among the conductive strips in a same layer, odd ones of the conductive strips are connected together, and even ones of the conductive strips are connected together,” into independent claims 1 and 20 fail to overcome the prior art of record. Lue2 teaches wherein the even conductive strips are connected together and wherein the odd conductive strips are connected together, as shown in Fig. 13. More details are given in the rejections of claims 1 and 20, below.
Claim Rejections - 35 USC § 112
The rejection under 35 U.S.C. 112(b) of 07/29/2025 has been addressed in the applicant remarks filed 10/17/2025, wherein the applicant states their intention to amend the language of claim 4 from “matches” to “comprises,” which would overcome the rejection. However, the claim has not been amended, thus the rejection under 35 U.S.C. 112(b) of claim 4 is maintained, but the examiner notes that the applicant intended to amend and for the purposes of examination, the claim language “comprises” will be considered. Accordingly, the rejection of dependent claim 5 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lue (US PGPub 2022/0013535), herein Lue, further in view of Lue (KR 2015/0134260, translation provided for citation), herein Lue2.
Regarding claim 1, Lue teaches (Figs. 1A-1I) a memory block, comprising: a memory array (10), comprising a plurality of stacked strip structures (Fig. 1A, 102) and a plurality of semiconductor structures (annotated Fig. 1I below, SS), the stacked strip structures being spaced apart from each other along a column direction (annotated Fig. 1I below, Col); and each of the stacked strip structures extending along a row direction (annotated Fig. 1I below, Row), and comprising a plurality of insulating strips (Fig. 1A, 104) and a plurality of conductive strips (Fig. 1A, 106) alternately stacked along a height direction; and wherein some of the semiconductor structures are arranged between every two adjacent stacked strip structures (Fig. 1I), the every two adjacent stacked strip structures and some of the semiconductor structures arranged therebetween are involved in forming a row of memory subarray, the conductive strips in the every two adjacent stacked strip structures serve as control gates (Fig. 1I, 126) of the row of memory subarray; the row of memory subarray comprises a plurality of memory-cell groups distributed along the row direction, each memory-cell group comprises a corresponding semiconductor structure, the corresponding semiconductor structure extends along the height direction ([0050]), and on a plane perpendicular to the height direction, a cross section of the corresponding semiconductor structure is ring-shaped ([0024]).
Lue does not explicitly teach wherein in the height direction, among the conductive strips in a same layer, odd ones of the conductive strips are connected together, and even ones of the conductive strips are connected together.
Lue2 teaches (Fig. 13, equivalent embodiment to Fig. 5a), wherein in the height direction, among the conductive strips in a same layer, odd ones (201, [0056]) of the conductive strips are connected together, and even ones of the conductive strips (200, [0056]) are connected together.
Because Lue and Lue2 are both directed toward stacked memory strip devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lue and Lue2 in order to form a double gate flash memory cell with high density data storage (Lue2, [0009]).
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Regarding claim 2, Lue in view of Lue2 teaches (Lue, Fig. 1I) the memory block according to claim 1, wherein in each memory-cell group, the corresponding semiconductor structure comprises a source-region semiconductor structure (Fig. 1I, 118, [0094]), a drain-region semiconductor structure (118, [0094]), a first channel semiconductor structure (112, [0094]), and a second channel semiconductor structure (112, [0094]); the first channel semiconductor structure and the second channel semiconductor structure are respectively arranged between the source-region semiconductor structure and the drain-region semiconductor structure ([0050]); and the source-region semiconductor structure, the drain-region semiconductor structure, the first channel semiconductor structure, and the second channel semiconductor structure extend along the height direction respectively ([0043]).
Regarding claim 3, Lue in view of Lue2 teaches (Lue, annotated Fig below) the memory block according to claim 2, wherein in each memory-cell group, the first channel semiconductor structure (SS1) and the second channel semiconductor structure (SS2) are bent in directions away from each other ([0043]).
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Regarding claim 4, Lue in view of Lue2 teaches (Lue, annotated Fig. 1I below) the memory block according to claim 2, wherein in two adjacent stacked strip structures (SSS1, SSS2) corresponding to each memory-cell group, each conductive strip serves as a control gate (126) of the memory-cell group, to form a memory cell; and the memory cell matches at least part of a corresponding conductive strip (126), a first/second channel semiconductor structure (112), the source-region semiconductor structure (118), and the drain-region semiconductor structure (118); in the column direction, one of the two adjacent stacked strip structures arranged at a first side of the memory-cell group serves as a first stacked strip structure corresponding to the memory-cell group, the other of the two adjacent stacked strip structures arranged at a second side of the memory-cell group serves as a second stacked strip structure corresponding to the memory-cell group, and the first side is opposite to the second side; each conductive strip in the first stacked strip structure (SSS1) serves as a first control gate of the memory-cell group ([0036]), to form a first memory cell (M1); and the first memory cell matches at least part of a corresponding conductive strip, the first channel semiconductor structure, the source-region semiconductor structure, and the drain-region semiconductor structure; and each conductive strip in the second stacked strip structure (SSS2) serves as a second control gate of the memory-cell group, to form a second memory cell (M1); and the second memory cell matches at least part of a corresponding conductive strip, the second channel semiconductor structure, the source-region semiconductor structure, and the drain-region semiconductor structure (annotated Fig. 1I below).
Regarding claim 5, Lue in view of Lue2 teaches the memory block according to claim 4, wherein each stacked strip structure at a non-edge region corresponds to two adjacent rows of memory subarrays; each conductive strip in each stacked strip structure at the non-edge region serves as the first control gate of each memory-cell group in one of the two adjacent rows of memory subarrays, to form the first memory cell, and serves as the second control gate of each memory-cell group in the other of the two adjacent rows of memory subarrays, to form the second memory cell. Lue does not explicitly teach wherein each conductive strip in each stacked strip structure serves as a word line.
Lue2 teaches (Fig. 5a) wherein each conductive strip (25, 26, 45, 46, 65) in each stacked strip structure (60-63) serves as a word line [0022].
Because Lue and Lue2 are both directed toward stacked strip memory devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lue and Lue2 to include wherein each conductive strip in each stacked strip structure serves as a word line in order to provide control of the memory device (Lue2, [0022]).
Regarding claim 6, Lue in view of Lue2 teaches (Lue, annotated Fig. 1I below) the memory block according to claim 2, wherein each memory-cell group corresponds to two adjacent stacked strip structures (SSS1, SSS2); and each memory-cell group further comprises a first memory structure (M1) and a second memory structure (M2); the first memory structure is arranged between the corresponding semiconductor structure (SS1) and one of the two adjacent stacked strip structures (SSS1), bending directions of the first memory structure and the first channel semiconductor structure are the same as each other (shown in annotated Fig. 1I below); the second memory structure is arranged between the corresponding semiconductor structure (SS2) and the other of the two adjacent stacked strip structures (SSS2), and bending directions of the second memory structure and the second channel semiconductor structure are the same as each other (shown in annotated Fig. 1I below).
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Regarding claim 7, Lue in view of Lue2 teaches (Lue, Fig. 1I) the memory block according to claim 6, wherein the first memory structure and the second memory structure are charge-trapping memory structures respectively ([0039]), and extend along the height direction respectively; the first memory structure is arranged between one of the two adjacent stacked strip structures (SSS1, SSS2) and the source-region semiconductor structure, the drain-region semiconductor structure (118), and the first channel semiconductor structure (112); and the second memory structure is arranged between the other of the two adjacent stacked strip structures and the source-region semiconductor structure (118), the drain-region semiconductor structure (112), and the second channel semiconductor structure; and each of the first memory structure and the second memory structure comprises a first dielectric layer ([0039], not pictured), a charge-trapping layer (110, [0039]), and a second dielectric layer ([0039], not pictured); the first dielectric layer is arranged between the charge-trapping layer and a corresponding stacked strip structures; the charge-trapping layer is arranged between the first dielectric layer and the second dielectric layer; and the second dielectric layer is arranged between the charge-trapping layer and the source-region semiconductor structure, the drain-region semiconductor structure, and a first/second channel semiconductor structure ([0039]).
Regarding claim 8, Lue in view of Lue2 teaches the memory block according to claim 6 wherein each of the first memory structure and the second memory structure comprises a plurality of floating-gate memory structures distributed along the height direction; and each of the floating-gate memory structures is involved in forming a memory cell; the first memory structure is arranged between one of the two adjacent stacked strip structures and the source-region semiconductor structure, the drain-region semiconductor structure, and the first channel semiconductor structure; the second memory structure is arranged between the other of the two adjacent stacked strip structures and the source-region semiconductor structure, the drain-region semiconductor structure, and the second channel semiconductor structure; and each floating-gate memory structure comprises a floating gate and an insulating dielectric layer wrapping the floating gate; in the memory cell, a floating-gate memory structure is arranged between a corresponding conductive strip and a first/second channel semiconductor structure; and any surface of the floating gate is coated by the insulating dielectric layer. Lue does not explicitly state wherein the conductive strip comprises a floating gate, however the structure of Lue, as shown in Fig. 1F, demonstrates conductive gate layers (106) surrounded by insulating layers (104), which forms a floating gate architecture.
Regarding claim 9, Lue in view of Lue2 teaches (Lue, Fig. 1I) the memory block according to claim 2, wherein in each memory-cell group, a first insulating structure (114, [0041]) is arranged in an annular region enclosed by the source-region semiconductor structure (118, [0067]), the drain-region semiconductor structure (118, [0067]), the first channel semiconductor structure (112, [0060]), and the second channel semiconductor structure (112, [0060]) cooperatively.
Regarding claim 10, Lue in view of Lue2 teaches (Lue, Fig. 1I) the memory block according to claim 2, wherein in the row direction, a second insulating structure (107, [0037]) is arranged between the source-region semiconductor (118) structure in one memory-cell group and the drain-region semiconductor structure (118) in an adjacent memory-cell group ([0037]).
Regarding claim 11, Lue in view of Lue2 teaches (Lue, Fig. 1I) the memory block according to claim 1, wherein the memory-cell groups in two adjacent rows of memory subarrays are misaligned with each other ([0098]).
Regarding claim 12, Lue in view of Lue2 teaches (Lue) the memory block according to claim 2, wherein the corresponding semiconductor structure in each memory-cell group further comprises a source-region-semiconductor connecting column (Fig. 2F, 222, [0069]), a drain-region-semiconductor connecting column (Fig. 2F, 222, [0069]), the source-region-semiconductor connecting column is connected to the source-region semiconductor structure (Fig. 2F, 218, [0069]); the drain-region-semiconductor connecting column is connected to the drain-region semiconductor structure (Fig. 2F, 218, [0069]). Lue in view of Lue2 does not explicitly teach wherein in the height direction, among the conductive strips in a same layer, odd ones of the conductive strips are connected together, and even ones of the conductive strips are connected together; a first channel-semiconductor connecting column, and a second channel-semiconductor connecting column extending along the height direction; in the height direction; the first channel-semiconductor connecting column is connected to the first channel semiconductor structure; and the second channel-semiconductor connecting column is connected to the second channel semiconductor structure; and in a plurality of rows of memory subarrays, source-region semiconductor structures of the memory-cell groups in a same row are connected to a same source line through corresponding source-region-semiconductor connecting columns; drain-region semiconductor structures of the memory-cell groups in a same column are connected to a same bit line through corresponding drain-region-semiconductor connecting columns; first channel semiconductor structures and second channel semiconductor structures of the memory-cell groups in the same column are connected to a same well-region line through corresponding first channel-semiconductor connecting columns and corresponding second channel-semiconductor connecting columns.
Lue2 teaches (Fig. 5a) a first channel-semiconductor connecting column (607, [0085]), and a second channel-semiconductor connecting column (607, [0085]) extending along the height direction; in the height direction; the first channel-semiconductor connecting column is connected to the first channel semiconductor structure ([0029]); and the second channel-semiconductor connecting column is connected to the second channel semiconductor structure ([0029]); and in a plurality of rows (60, 61, 62, 63) of memory subarrays, source-region semiconductor structures of the memory-cell groups in a same row are connected to a same source line (30, [0025]) through corresponding source-region-semiconductor connecting columns; drain-region semiconductor structures of the memory-cell groups in a same column are connected to a same bit line through corresponding drain-region-semiconductor connecting columns ([0028]); first channel semiconductor structures and second channel semiconductor structures of the memory-cell groups in the same column are connected to a same well-region line through corresponding first channel-semiconductor connecting columns and corresponding second channel-semiconductor connecting columns ([0028]).
Because Lue and Lue2 are both directed toward stacked memory strip devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lue and Lue2 in order to form a double gate flash memory cell with high density data storage (Lue2, [0009]).
Regarding claim 20, Lue teaches a memory device, comprising one or more memory blocks, wherein each memory block comprises: a memory array (annotated Fig. 1I below, 10), comprising a plurality of stacked strip structures (annotated Fig. 1I below, 126) and a plurality of semiconductor structures (annotated Fig. 1I below, SS), the stacked strip structures being spaced apart from each other along a column direction (annotated Fig. 1I below, Col); and each of the stacked strip structures extending along a row direction (annotated Fig. 1I below, Row), and comprising a plurality of insulating strips (Fig. 1A, 104) and a plurality of conductive strips (Fig. 1A, 106) alternately stacked along a height direction; and wherein some of the semiconductor structures are arranged between every two adjacent stacked strip structures ([0050]), the every two adjacent stacked strip structures and some of the semiconductor structures arranged therebetween are involved in forming a row of memory subarray, the conductive strips in the every two adjacent stacked strip structures serve as control gates of the row of memory subarray ([0036]); the row of memory subarray comprises a plurality of memory-cell groups distributed along the row direction, each memory-cell group comprises a corresponding semiconductor structure (annotated Fig. 1I below, SS), the corresponding semiconductor structure extends along the height direction, and on a plane perpendicular to the height direction, a cross section of the corresponding semiconductor structure is ring-shaped ([0037]).
Lue does not explicitly teach wherein in the height direction, among the conductive strips in a same layer, odd ones of the conductive strips are connected together, and even ones of the conductive strips are connected together.
Lue2 teaches (Fig. 13, equivalent embodiment to Fig. 5a), wherein in the height direction, among the conductive strips in a same layer, odd ones (201, [0056]) of the conductive strips are connected together, and even ones of the conductive strips (200, [0056]) are connected together.
Because Lue and Lue2 are both directed toward stacked memory strip devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lue and Lue2 in order to form a double gate flash memory cell with high density data storage (Lue2, [0009]).
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lue in view of Lue2 as applied to claim 12 above, and further in view of Baek et al. (US PGPub 2022/0157831), herein referred to as Baek.
Regarding claim 13, Lue in view of Lue2 teaches the memory block according to claim 12, but does not explicitly teach wherein the source-region-semiconductor connecting column in each memory-cell group is further sleeved with a source-region conductive controlling ring; and source-region conductive controlling rings of the memory-cell groups in the same column are connected to a same source controlling line; and the drain-region-semiconductor connecting column in each memory-cell groups is further sleeved with a drain-region conductive controlling ring; and drain-region conductive controlling rings of the memory-cell groups in the same column are connected to a same bit-line controlling line.
Lue in view of Lue2 teaches a source-region and drain-region semiconductor connecting column in each memory cell, and teaches wherein each source-region and drain-region are connected to control lines (Lue2, [0032]). Luo in view of Lue2 does not specify the method of connection between the source-region and drain-region connecting columns and the control lines.
Baek teaches (Fig. 4C) a columnar contact (CC) in a stacked memory device with a ring-shaped sleeve contact (CP2) used to aid in connection between the columnar contact and a connection lines ([0104]).
One of ordinary skill in the art would have recognized that combination of the teachings of Lue in view of Lue2 and of Baek would have predictably formed an electrical connection between the connecting column and the control lines, therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lue in view of Lue2 and of Baek to enable wherein the source-region-semiconductor connecting column in each memory-cell group is further sleeved with a source-region conductive controlling ring; and source-region conductive controlling rings of the memory-cell groups in the same column are connected to a same source controlling line; and the drain-region-semiconductor connecting column in each memory-cell groups is further sleeved with a drain-region conductive controlling ring; and drain-region conductive controlling rings of the memory-cell groups in the same column are connected to a same bit-line controlling line.
Regarding claim 14, Lue in view of Lue2 and Baek teaches (Lue2, Fig. 5a) the memory block (entire array, [0010]) according to claim 13, and Lue in view of Lue2 further teaches wherein the memory block is configured to receive a control signal and execute the following operations: selecting all the odd or even ones of the conductive strips in one layer to apply a first word-line selecting voltage and executing a layer selection; selecting one bit line to apply a first bit-line selecting voltage and executing a column selection; and selecting one source line to apply a first source selecting voltage, executing a row selection, and selecting one memory cell to execute a read operation in coordination with the layer selection and the column selection ([0010, 0063]).
Regarding claim 15, Lue in view of Lue2 and Baek teaches (Lue2, Fig. 5a) the memory block (entire array, [0010]) according to claim 13, and Lue in view of Lue2 further teaches wherein the memory block is configured to receive a control signal and execute the following operations: selecting all the odd or even ones of the conductive strips in one layer to apply a second word-line selecting voltage and executing a layer selection; selecting one source line to apply a second source selecting voltage and executing a row selection; selecting one source controlling line, applying no source controlling voltage to the selected source controlling line, applying the source controlling voltage to other source controlling lines, and executing a column selection; and selecting a bit-line controlling line to apply a bit-line controlling voltage, and selecting one memory cell to execute a programming operation in coordination with the layer selection, the row selection, and the column selection; and the selected bit-line controlling line and the selected source controlling line being connected to the memory-cell groups in the same column ([0063]).
Regarding claim 16, Lue in view of Lue2 and Baek teaches (Lue2, Fig. 5a) the memory block (entire array, [0010]) according to claim 13, and Lue in view of Lue2 further teaches wherein well-region lines of the memory block are connected together; the memory block is configured to receive a control signal and execute the following operations: selecting all the odd or even ones of the conductive strips in each layer to apply a third word-line selecting voltage; and applying an erasing voltage to all the well-region lines to execute an erasing operation on memory cells formed with a participation of all the odd or even ones of the conductive strips in each layer ([0073]).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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/EMILY FARMER/Examiner, Art Unit 2812
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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