DETAILED ACTION
Claims 1-10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure submitted on November 12, 2025, is objected to because of the following informalities:
In paragraphs 98 and 100, replace each instance of “SB 1” with --SB1--.
Appropriate correction is required.
Drawings
Original FIGs 1-5, 8-10, and 12-16 are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated, likely because applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. This cannot be confirmed with certainty since the examiner does not have access to applicant’s submitted pdf file. However, it is the examiner’s experience that pixelation usually occurs when black is not being used. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
In claims 1 and 10, last paragraph, the examiner recommends replacing each instance of “first to third” with --first, second, and third--.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 1, applicant claims that based on a third instruction including interrupt information, second data is transmitted. In FIG.12, the instruction that includes interrupt information is instruction 6. However, this instruction doesn’t cause transmission of the second data. As the examiner understands the invention, it is instructions 3-1, 3-2, and 3-3, which don’t include interrupt information, in FIG.12 that cause the second data to be transmitted. As such, the claim appear to include new matter.
Claim 10 is rejected for similarly including new matter. That is, the examiner cannot find original support for a third instruction that stores a third piece to the second memory, wherein the third instruction includes interrupt information.
Claims 2-9 are rejected due to its dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 2, “the instruction set describing…”. Applicant never previously set for an instruction set that describes anything.
In claim 6, “the first and second instructions” because this could refer to the first and second instructions in claim 1 or to the first instructions and second instructions of claim 5.
Claim 3-8 are rejected due to its dependence on an indefinite claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 3 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends. Specifically, claim 3 sets forth that the last instruction is related to the second partial data. However, parent claim 1 sets forth that the third instruction is the last instruction and that the third instruction transmits the second partial data. Thus, there is already relation established between the third/last instruction and the second partial data, and, therefore, claim 3 does not appear to add any limitation beyond that which is already in claim 1. Applicant may cancel claim 3, amend it to be proper dependent form, or present a sufficient showing that it complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Parker, U.S. Patent Application Publication No. 2020/0125294, in view of Ko, KR 20030039644 (a Google translation of which is provided herewith).
Referring to claim 1, Parker has taught a memory system comprising:
a first die (FIG.4, 110-1) including a non-interleaving block group (the group of memory blocks in the left plane 10 in 110-1 written to with data 52A);
a second die (FIG.4, 110-2) including an interleaving block group (the group of memory blocks in 110-2 written to with data 52B. This group may be called an interleaving group because it is written to in between portions of another group); and
a memory controller configured to:
based on a first instruction, transmit first partial data of first data from a buffer memory to the first die to program the first partial data into the non-interleaving block group (see paragraph 46. Data to be written is cached/buffered. From the cache/buffer, first partial data of first data 52A is written to the left plane 10 in 110-1. This would occur in response to some first instruction instructing this left plane to be written),
based on a second instruction, transmit, after transmitting the first partial data, second data from the buffer memory to the second die to program the second data into the interleaving block group (see paragraph 46. After the first partial data is transmitted, second data 52B is written to the left plane 10 in 110-1 and to planes in die 110-2 (note from paragraph 43 that a data stream is written to multiple dies in a superblock, e.g. 50B, concurrently/simultaneously. This would occur in response to some second instruction instructing the superblock be written),
based on a third instruction, transmit, after transmitting the second data, second partial data of the first data from the buffer memory to the first die to program the second partial data into the non-interleaving block group (see paragraph 46. After the second data 52B is transmitted, second partial data of first data 52A is written to the left plane 10 in 110-1. This would occur in response to some first instruction instructing this left plane to be written),
wherein the first to third instructions are included in an instruction set sequentially performed by the memory controller and the third instruction is a last instruction among instructions in the instruction set (again, the three different writes are sequentially performed and thus the three instructions for a sequential set of instructions to be executed to carry out these different writes. The third instruction is the last of this group),
Parker has not taught that the memory controller is configured to generate an interrupt based on interrupt information upon completion of performance of the third instruction, and in response to the interrupt, erase, after transmitting the second partial data, the first and second data stored in the buffer memory. However, Ko has taught generating an interrupt to erase data from a transmission buffer when all data transmission completes, e.g. after the final instruction (see the top of p.2 above the “Description” in the attached translation). This is useful to allow other data to be stored in the buffer and/or for increased security (if the data exists in one less place, that is one less place that is susceptible to attack to try to obtain data). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Parker such that the memory controller is configured to generate an interrupt based on interrupt information upon completion of performance of the third instruction, and in response to the interrupt, erase, after transmitting the second partial data, the first and second data stored in the buffer memory, i.e., the cache of Parker.
Parker, as modified, has further taught the third instruction including the interrupt information (the interrupt information is broadly claimed. As disclosed by Ko, the interrupt occurs after all data is transmitted. Thus, the third instruction, which transmits the last of the data, includes interrupt information, i.e., the last data to be transmitted, such that in response to that information being in the third instruction, causes the interrupt to occur).
Referring to claim 2, Parker, as modified, has taught the memory system of claim 1, wherein the memory controller comprises a memory interface configured to: configure the instruction set describing a procedure for sequentially programming the first and second data (from paragraph 46, there are separate instructions generated to transmit the data sequentially); and sequentially perform instructions in the instruction set, to transmit the first and second data to the first and second dies (instructions are executed/performed to carry out data transmission).
Referring to claim 3, Parker, as modified, has taught the memory system of claim 2, wherein the last instruction is related to the second partial data (the data transmission in paragraph 46 of Parker ends with the second partial data (in association with the last instruction).
Referring to claim 5, Parker, as modified, has taught the memory system of claim 2, wherein the memory interface separately configures first instructions corresponding to the first partial data and second instructions corresponding to the second partial data (again, from paragraph 46, there must be instructions associated with each sequential transmission so as to transmit different data at different times).
Referring to claim 6, Parker, as modified, has taught the memory system of claim 5, wherein the memory interface configures third instructions corresponding to the second data separately from the first and second instructions (again, from paragraph 46, there must be instructions associated with each sequential transmission so as to transmit different data at different times. Transmitting the first partial data to first locations will require a first set of instructions. Transmitting the second partial data to second locations will require a second set of instructions. And, transmitting the second data to third locations will requires a third set of instructions).
Referring to claim 7, Parker, as modified, has taught the memory system of claim 6, wherein the memory interface configures the instruction set such that the second instructions are set to be performed after the third instructions (see paragraph 46. This third instructions that store data 52B occur between the first and third instructions that store parts of data 52A).
Referring to claim 8, Parker, as modified, has taught the memory system of claim 5, wherein the memory interface accesses the first die according to the first instructions (paragraph 46) and the second instructions (paragraph 46), and holds performance of a separate instruction that is not included in the instruction set before performance of the second instructions is completed (the erasing is not performed until all data is transmitted. Thus, the erasing is held until after at least the second instructions are completed).
Referring to claim 9, Parker, as modified, has taught the memory system of claim 1, wherein memory blocks of the non-interleaving block group are included in the same plane of the first die (as described in the rejection of claim 1, the memory blocks of the non-interleaving group are in leftmost plane 10 (in die 110-1)), and wherein memory blocks of the interleaving block group are included in different planes of the second die (see FIG.4, and note the two planes in die 110-2, which are written to with data 52B. These make up the interleaving group).
Referring to claim 10, Parker has taught a memory system comprising:
a memory device including first and second dies (FIG.4, dies 110-1 and 110-2) sharing a single channel (from paragraph 46, the data to be written to both dies comes from the same cache/buffer. Thus, there is a shared channel, i.e., connection from cache to dies. Alternatively, from paragraph 43, both dies would share a data stream channel because they can both be written with data from the same data stream simultaneously. Thus, in FIG.4, because the two dies can be written at the same time with data 52A, the dies share a 52A channel), the first die including first and second memory blocks within a single plane of the first die (from FIG.4, leftmost plane 10 includes a first block for data from stream 52A and a second block for data from stream 52B), and the second die including a group of memory blocks within different planes of the second die (from FIG.4, a group of memory blocks span the two planes therein);
a buffer configured to buffer first to third pieces of data (paragraph 46, cache (which buffers data while the sequential transmission occurs)); and
a memory controller configured to:
control the memory device to perform a program operation of sequentially storing the first to third pieces respectively into the first memory block, the group and the second memory block (paragraph 46), based on a first instruction, a second instruction, and a third instruction (each different write in paragraph 46 would correspond to a different instruction (e.g. see the rejection of claim 1)), wherein the program operation is performed on the group according to a plane interleaving scheme (from paragraph 46, because data 52A and 52B are written to the same plane, the group of memory blocks to hold data from 52B are operated on according to an interleaving scheme (where the write of data 52B interleaves with the writes of data 52A),
wherein the first to third instructions are included in an instruction set sequentially performed by the memory controller and the third instruction is a last instruction among instructions in the instruction set (again, the three different writes are sequentially performed and thus the three instructions for a sequential set of instructions to be executed to carry out these different writes. The third instruction is the last of this group).
Parker has not taught that the memory controller is configured to generate an interrupt based on interrupt information upon completion of performance of the third instruction; and in response to the interrupt, remove the first to third pieces from the buffer. However, Ko has taught generating an interrupt to erase data from a transmission buffer when all data transmission completes (see the top of p.2 above the “Description” in the attached translation). This is useful to allow other data to be stored in the buffer and/or for increased security (if the data exists in one less place, that is one less place that is susceptible to attack to try to obtain data). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Parker such that the memory controller is configured to generate an interrupt based on interrupt information upon completion of performance of the third instruction; and in response to the interrupt, remove the first to third pieces from the buffer, i.e., the cache of Parker.
Parker, as modified, has further taught the third instruction including the interrupt information (the interrupt information is broadly claimed. As disclosed by Ko, the interrupt occurs after all data is transmitted. Thus, the third instruction, which transmits the last of the data, includes interrupt information, i.e., the last data to be transmitted, such that in response to that information being in the third instruction, causes the interrupt to occur).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Parker in view of Ko and the examiner’s taking of Official Notice.
Referring to claim 4, Parker, as modified, has taught the memory system of claim 3, wherein the memory controller is configured to erase the first and second data stored in the buffer memory when the interrupt is received from the memory interface (as explained above, Ko generates an interrupt to perform the erasing. Whichever component receives the interrupt and erases is part of the memory controller). Parker has not taught that the memory controller comprises a central processing unit that is configured to perform the erasing. However, Official Notice is taken that a memory controller including a CPU and a CPU responding to an interrupt were well known in the art before applicant’s invention. Implementing a CPU in a memory controller provides the memory controller with more power to perform various tasks. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Parker such that the memory controller comprises a central processing unit that is configured to perform the erasing.
Response to Arguments
On pages 8-9 of applicant’s response, applicant notes that FIGs.6-7 and 11 were objected to and replacements therefor have been filed.
The examiner notes that all FIGs were objected to (not just FIGs.6-7 and 11) and, thus, replacements are still needed for the remaining originals.
On page 14 of applicant’s response, applicant argues that Parker does not disclose which write among streams 52A-52B constitutes the last write.
The examiner respectfully disagree and notes that paragraph 46 of Parker sets forth write execution swapping back and forth. Thus, writing of a second part of 52A comes last among the three writes in the example of paragraph 46.
Applicant also argues on pages 14-15 of the response, that the last instruction is not taught to include interrupt information in Parker or Ko.
The examiner again notes the breadth of the interrupt information claimed. As explained in the rejection, in the combination of prior art, the interrupt is generated in response to the last write. Thus, the last instruction being the last write includes interrupt information (e.g. the final data to be written, or the final write opcode, etc.). In response to this, the interrupt will be generated.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights