Detailed Action
This office action is in response to the amendment filed on January 2nd, 2026. Claims 1-7 and 21-33 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed January 2nd, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 8-11, “Remarks”) that Smith and the other cited references fail to teach limitations presented in Claims 1, 21, and 30. Smith does not disclose that channel regions 124, 126, and 130 are field effect transistors. Instead, Smith describes channel regions 124, 126, and 130 as top channel region, bottom channel region, and plurality of gate structures. Further, in figure 2B of Smith, it is seen that channel regions 124, 126, and 130 are part of the device 100 which is a complementary field effect transistor. Thus, there are no suggestions or teachings of two FETs which are stacked. Additionally, Smith merely describes that a top source/drain is staggered over bottom source/drain in a pre-metal dielectric layer. However, Smith fails to disclose that the top source/drain and the bottom source/drain are in electrical contact with the top FET and bottom FET.
Examiner notes that Smith teaches that the device is a complementary FET and is a standard cell in which either NMOS or PMOS is positioned over its complement ([0048]). In other words, the device consists of a n-type MOSFET stacked over a p-type MOSFET or vice versa. Additionally, the cited top source/drain (104a) surrounds (see fig. 2B) and contacts the channel region (126) of the top FET (126, 130). Similarly, the cited bottom source/drain (102a) surrounds (see fig. 2B) and contacts the channel region (122) of the bottom FET (124, 130). Furthermore, both source/drain (102a, 104a) are described as PMOS or NMOS source/drains ([0056]) and both channel regions (124, 126) are described to be PMOS or NMOS channel regions ([0064]). As a result, it is clear that the top and bottom source/drains are in electrical contact with the top and bottom FET as described in the rejection below.
Therefore, applicant’s arguments are not persuasive.
Claim Objections
Claim 28 is objected to because of the following informalities:
The claim recites the limitation “backside power distribution rail” in line 3. The limitation will be interpreted as “a backside power distribution rail”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 21-26, and 28-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith et al. (2019/0288004 A1; hereinafter Smith).
Regarding Claim 1, Smith (fig. 2A and annotated fig. 2B) teaches a semiconductor device ([0056], 100) comprising:
a first stacked field effect transistor (FET), ([0064]-[0065], 124, 126, 130 see annotated fig. 2B), comprising: a top FET (126, 130) that is disposed above a bottom FET (124, 130), and in electrical contact with a top source/drain epitaxial (SID epi) ([0056], 104a) and a back end of line (BEOL) interconnect ([0059], the BEOL interconnect comprises the metal interconnects positioned above 134, including 122a-122c, see fig. 2A, and including the unmarked gate contacts positioned above 134, labeled BEOL interconnect, see annotated fig 2B); and
the bottom FET (124, 130), wherein the bottom FET (124, 130) is in electrical contact with a bottom SID epi ([0056], 102a);
a shallow backside contact ([0056], 106a) that is in electrical contact with the bottom SID epi (102a); and
a first deep via ([0059], 118a) that is in electrical contact with the BEOL interconnect (122a) and the shallow backside contact (106a), wherein the first deep via (118a) and the shallow backside contact (106a) provide a conductive path between the BEOL interconnect (122a) and the bottom SID epi (102a).
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Annotated Figure 2B
Regarding Claim 2, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 1, further comprising a second deep via ([0058], 116a) that is in electrical contact with a top source/drain contact ([0056], 108a) and a backside power rail (BSPR) ([0058], 114a-d, connected to 114b).
Regarding Claim 3, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 2, further comprising a frontside contact (portion of unmarked gate contacts positioned below 134, labeled frontside contact, see annotated fig. 2B) between the top FET (126, 130) and the BEOL interconnect (BEOL interconnect).
Regarding Claim 4, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 1, wherein a depth of the shallow backside contact (106a) prevents a short to a backside power rail (BSPR) ([0058], 114b).
Regarding Claim 5, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 4, further comprising a deep backside contact ([0056], 106b), wherein the deep backside contact (106b) is in electrical contact with a second bottom FET ([0056], 102b) and the BSPR (114a-d, connected to 114c).
Regarding Claim 21, Smith (fig. 2A and annotated fig. 2B) teaches a semiconductor device ([0056], 100) comprising:
a first stacked transistor ([0064]-[0065], 102a, 104a, 124, 126, 130 see annotated fig. 2B) comprising a first top transistor (104a, 126, 130) stacked over a first bottom transistor (102a, 124, 130), the first bottom transistor (102a, 124, 130) comprising a first bottom source/drain region (102a);
a second stacked transistor ([0064]-[0065], 102b, 104b, 124, 126, 130 see annotated fig. 2B) comprising a second top transistor (104b, 126, 130) stacked over a second bottom transistor (102b, 124, 130), the second bottom transistor (102b, 124, 130) comprising a second bottom source/drain region (102b);
a first backside contact ([0056], 106a) in direct contact with the first bottom source/drain region (102a); and
a second backside contact ([0056], [0058], 106b, portion of 116b positioned above 120c) in direct contact with the second bottom source/drain region (102b), wherein a bottommost backside surface of the second backside contact (bottom surface of 116b positioned above 120c, see fig. 2A) is below a bottommost backside surface of the first backside contact (bottom surface of 106a, see fig. 2A).
Regarding Claim 22, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 21, further comprising: a backside power distribution network ([0058], 114a-d) electrically connected to the bottommost backside surface of the second backside contact (116b is connected to 114c).
Regarding Claim 23, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 22, wherein the first top transistor (104a, 126, 130) comprises a first top source/drain region (104a) and wherein the semiconductor device further includes a first frontside contact ([0056], 108a) in direct contact with the first top source/drain region (104a).
Regarding Claim 24, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 23, wherein the second top transistor (104b, 126, 130) comprises a second top source/drain region (104b) and wherein the semiconductor device further includes a second frontside contact ([0056], 108b) in direct contact with the second top source/drain region (104b).
Regarding Claim 25, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 24, further comprising: a frontside back end of line (BEOL) network ([0059], the BEOL network comprises the metal interconnects positioned above 134, including 122a-122c, see fig. 2A) in electrical contact ([0080]-[0081], annotated fig. 5A is an additional cross-sectional view of the features described in fig. 2A and shows 108a in contact with the BEOL network) with the first frontside contact (108a).
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Annotated Figure 5A
Regarding Claim 26, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 25, further comprising: a first deep backside contact ([0059], 118a) in direct contact with the first backside contact (106a) and in electrical contact with the frontside BEOL network (122a).
Regarding Claim 28, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 26, further comprising: a second deep backside contact (portion of 116b positioned below 120c, labeled second deep backside contact, see annotated fig. 2A) in direct contact with the second backside contact (106b, portion of 116b positioned above 120c) and in electrical contact with backside power distribution rail (114c).
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Annotated Figure 2A
Regarding Claim 29, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 28, wherein the second deep backside contact (second deep backside contact) is also in electrical contact ([0080]-[0081], annotated fig. 5A is an additional cross-sectional view of the features described in fig. 2A and shows 106b in contact with the BEOL network) with the frontside BEOL network (BEOL network).
Regarding Claim 30, Smith (fig. 2A and annotated fig. 2B) teaches a semiconductor device ([0056], 100) comprising:
a first bottom transistor ([0064]-[0065], 102a, 124, 130, see annotated fig. 2B) comprising a first bottom source/drain region (102a);
a second bottom transistor ([0064]-[0065], 102b, 124, 130, see annotated fig. 2B) comprising a second bottom source/drain region (102b);
a first backside contact ([0056], 106a) in direct contact with the first bottom source/drain region (102a); and
a second backside contact ([0056], [0058], 106b, 116b) in direct contact with the second bottom source/drain region (102b), wherein a bottommost backside surface of the second backside contact (bottom surface of 116b in contact with 114b, see fig. 2A) is below a bottommost backside surface of the first backside contact (bottom surface of 106a, see fig. 2A).
Regarding Claim 31, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 30, further comprising: a backside power distribution network ([0058], 114a-d) electrically connected to a bottommost backside surface of the second backside contact (116b is connected to 114b).
Regarding Claim 32, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 31, further comprising: a backside interlayer dielectric (ILD) ([0056], 132) that adequately electrically separates the first backside contact (106a) from the backside power distribution network (114a-d).
Regarding Claim 33, Smith (fig. 2A and annotated fig. 2B) teaches the semiconductor device of claim 32, wherein the backside ILD (132) is directly upon respective sidewalls of the second backside contact (sidewalls of 106a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Smith as applied to Claim 5 above, and further in view of Hwang et al. (KR 20240020393 A; hereinafter Hwang).
Regarding Claim 6, Smith doesn’t explicitly teach the semiconductor device of claim 5, further comprising a gate cut region disposed between a first gate and a third gate, wherein the gate cut region is filled with bi-layer dielectrics.
However, Hwang (fig. 45) teaches a gate cut region ([0143], GC51) disposed between a first gate ([0039], UG1) and a third gate ([0039], UG2), wherein the gate cut region (GC51) is filled with bi-layer dielectrics ([0144], GC51 comprises GC51_1 and GC51_2). Hwang also teaches that gate cuts filled with dielectric materials isolate adjacent gate electrodes ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Smith to include the gate cuts of Hwang to isolate adjacent gates electrodes.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Smith and Hwang as applied to Claim 6 above, and further in view of Lin et al. (2022/0216340 A1; hereinafter Lin).
Regarding Claim 7, Smith doesn’t teach the semiconductor device of claim 6, further comprising a deep frontside contact that shorts a second bottom SID epi and a second top SID epi.
However, Lin (fig. 20) teaches a deep frontside contact ([0037], 278) that shorts a second bottom SID epi ([0037], 228-2) and a second top SID epi ([0037], 248-2). Lin also teaches that this provides the local electrical connection needed for some logic operations ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Smith to include the deep frontside contact of Lin to allow the use of some logic operations.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Smith as applied to Claim 26 above, and further in view of Park et al. (2023/0146060 A1; hereinafter Hwang).
Regarding Claim 27, Smith doesn’t teach the semiconductor device of claim 26, wherein the first deep backside contact is in direct contact with a sidewall of the first backside contact.
However, Park (fig. 4C) teaches the first deep backside contact ([0079], VEP) is in direct contact with a sidewall of the first backside contact ([0079], sidewall of HEP). Park also teaches that this allows for vertically stacked NMOS and PMOS-FETs with high reliability ([0172]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Smith to include the sidewall contact of Park to allow for vertically stacked NMOS and PMOS-FETs.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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