DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-10 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/4/2026.
Applicant’s election without traverse of claims 1-5 and 11-15 in the reply filed on 5/4/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Droege et al. (US 2013/0293292) (“Droege”) in view of Zhen et al. (US 2021/0296323) (“Zhen”).
With regard to claim 1, fig. 3 of Droege discloses an integrated circuit structure, comprising: an SRAM layer 314; a DRAM layer 318 vertically spaced apart from the SRAM layer 314; and a metallization structure 316 between the SRAM layer314 and the DRAM layer 318.
Droege does not disclose an SRAM layer comprising nanowire-based transistors
However, fig. 1 of Zhen discloses an SRAM layer (“SRAM cells”, par [0038]) comprising nanowire-based transistors (“nanowire transistors”, par [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the SRAM layer of Droege with the nanowire transistors as taught in Zhen in order to provide the ability to fine tune the drive strength of individual transistors allows for a better balance between read stability and write-ability without the need for assist circuitry. See par [0038] of Zhen.
With regard to claim 2, fig. 3 of Droege discloses that the SRAM layer 314 is above a substrate 310, and the DRAM layer 318 is above the SRAM layer 106.
With regard to claim 3, fig. 3 of Droege discloses a second metallization structure 320 above the DRAM layer 318.
With regard to claim 11, fig. 3 of Droege discloses a computing device, comprising: a board 310; and a component (314, 316, 318, 320) coupled to the board 310, the component (314, 316, 318, 320) including an integrated circuit structure (314, 316, 318, 320), comprising: an SRAM layer 314; a DRAM layer 318 vertically spaced apart from the nanowire-based transistors of the SRAM layer; and a metallization structure 316 between the SRAM layer 314 and the DRAM layer 318.
Droege does not disclose an SRAM layer comprising nanowire-based transistors
However, fig. 1 of Zhen discloses an SRAM layer (“SRAM cells”, par [0038]) comprising nanowire-based transistors (“nanowire transistors”, par [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the SRAM layer of Droege with the nanowire transistors as taught in Zhen in order to provide the ability to fine tune the drive strength of individual transistors allows for a better balance between read stability and write-ability without the need for assist circuitry. See par [0038] of Zhen.
With regard to claim 12, fig. 3 of Droege discloses a memory 312 coupled to the board 310.
With regard to claim 14, fig. 3 of Droege discloses that the component (314, 316, 318, 320) is a packaged integrated circuit die (“three-dimensional modules”, par [0015]).
With regard to claim 15, fig. 3 of Droege discloses that the component (314, 316, 318, 320) is selected from the group consisting of a processor (“processors”, par [0042]), a communications chip, and a digital signal processor.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Droege et al. (US 2013/0293292) (“Droege”), Zhen et al. (US 2021/0296323) (“Zhen”), and Bertin et al. (US 5,502,333) (“Bertin”).
With regard to claim 4, fig. 3 of Droege discloses that the DRAM layer 110 is above a substrate 102, and the SRAM layer is above the DRAM layer.
Droege and Zhen do not disclose that the SRAM layer is above the DRAM layer.
However, fig. 4a of Bertin discloses that the SRAM layer (“logic/SRAM chip 116 “, col. 8 ll. 6-7) is above the DRAM layer (“DRAM chips”, col 7 ll. 67).
Therefore, it would have been obvious to one of ordinary skill in the art to form the DRAM layer of Droege with the SRAM chip as taught in Bertin in order to provide substitute memory cells for failed memory cells in the stack. See col. 8 ll. 22-23 of Bertin.
With regard to claim 5, Droege and Zhen do not disclose a second metallization structure above the SRAM layer.
However, fig. 4a of Bertin discloses a second metallization structure 122 above the SRAM layer 116.
Therefore, it would have been obvious to one of ordinary skill in the art to form the DRAM layer of Droege with the SRAM chip connected with a wire bond as taught in Bertin in order to provide substitute memory cells for failed memory cells in the stack. See col. 8 ll. 22-23 of Bertin.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Droege et al. (US 2013/0293292) (“Droege”), Zhen et al. (US 2021/0296323) (“Zhen”), and Elsherbini et al. (US 2021/0098440) (“Elsherbini”).
With regard to claim 13, Droege and Zhen do not disclose a communication chip coupled to the board.
However, fig. 8 of Elshierbini discloses a communication chip 806 coupled to the board 802.
Therefore, it would have been obvious to one of ordinary skill in the art to form the 3D stacked modules of Droege with the communication chip as taught in Elsherbini in order to enable wireless communications for the transfer of data to a from the computing device. See par [0100] of Elsherbini.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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