DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-5, 7-11, 14 and 21-26 are pending in this application.
Prior drawing objection is withdrawn in view of cancellation of claims 6 and 13.
Specification
The amendment filed 12/29/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
Fig. 9B was newly added in the reply filed 12/29/2025. Fig. 9B shows a vertical cross-section of the region 166D in the z-x plane. However, it appears that the relationship between the layers 141, 142A, 160A, 163A and 166C, and their patterns and arrangements as viewed in the z-x plane is not supported by the originally filed specification, thus adding new matter.
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
The drawings are objected to under 37 CFR 1.83(a).
Fig. 9B was newly added in the reply filed 12/29/2025. Fig. 9B shows a vertical cross-section of the region 166D in the z-x plane. However, it appears that the relationship between the layers 141, 142A, 160A, 163A and 166C, and their patterns and arrangements as viewed in the z-x plane is not supported by the originally filed specification, thus adding new matter.
Claim 26 recites the limitation wherein, “wherein the second section of the GLS structure further includes a third dielectric layer configured between adjacent first dielectric layers, and the third dielectric layer is configured adjacent to a channel hole structure.” There is no figure showing a vertical cross-section of the second section of GLS structure (166C, Fig. 10), after the final device has been formed. It should be noted that Fig. 9A is an intermediate step and not the final device as required by claim 1, which requires a conductor/insulator stack as seen in Figs. 23/24. Examiner notes that the first dielectric layer is 141 and the second dielectric has to be 142A (for detailed explanation on the mapping, see 112(a) rejections of claim 25 and 26 below). The only remaining third dielectric layer that is configured between adjacent first dielectric layers in Fig. 9A is the sacrificial layer 142. Layer 142 will be etched and removed to form the conducting layer 145 of the stack (paras [0050] – [0057], Fig. 24) and there is no figure to show that a part of layer 142 will still be remaining in the second section 166C, after the formation of the conductor/insulator stack. Therefore, the limitation must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 7, 8 and 14 are objected to because of the following informalities:
Claims 7 and 14 recite the limitation, where, “the first section is between the second section and the fourth –second-- along the first direction” in line 3.
Examiner believes that the limitation should recite, “the first section is between the second section and the fourth --section-- along the first direction”.
Claim 8 recites the limitation, where, “the second dielectric layer in the second section is in contact with the first section along the first direction, respectively.” in line 13. Examiner believes that the limitation should recite, “the second dielectric layer in the second section is in contact with the first section along the first direction”, and “-- respectively --” should be removed.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 25 and 26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 25 recites the limitation wherein, “the first dielectric layer in the second section has a length greater than the second dielectric layer along a second direction perpendicular to the first direction.” As defined in claim 1, the second section is 166C (Fig. 9A), the first dielectric layer has to be 141 as it is part of the gate stack (Fig. 9A and Figs. 23-24), the second dielectric has to be 142A (Fig. 9A and newly added Fig. 9B), as the second dielectric has to contact 1st and 3rd sections (160A and 163A, respectively, see newly added Fig. 9B) as defined in claim 1. Now, claim 25 recites that a length of the first dielectric layer 141 is greater than a length of the second dielectric layer 142A in the region 166C, in a second direction perpendicular to the first direction (first direction is x-axis, see claim 1). This not supported in the specification or in the drawings. For example, in Fig. 9A, the length of 141 (marked “L1A” in annotated Fig. 9A below) is smaller than a length of 142A (marked “L2A” in annotated Fig. 9A below) along y-axis. Similarly, along z-axis also in Fig. 9A, there is no support to show that the vertical length of 141 (marked “L1B” in annotated Fig. 9A below) is greater than a vertical length of 142A (marked “L2B” in annotated Fig. 9A below). Thus, claim 25 is not supported by any specification or drawings, thus introducing new matter, and hence rejected.
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Claim 26 recites the limitation wherein, “wherein the second section of the GLS structure further includes a third dielectric layer configured between adjacent first dielectric layers, and the third dielectric layer is configured adjacent to a channel hole structure.” As explained, in the 112(a) rejection of claim 25 above, the second section of the GLS structure is 166C (Fig. 9A), the first dielectric layer has to be 141 (Fig. 9A and Figs. 23-24) and the second dielectric has to be 142A (Fig. 9A). The only remaining third dielectric layer that is configured between adjacent first dielectric layers in Fig. 9A is the sacrificial layer 142. It should be noted that Fig. 9A is an intermediate step and not the final device as required by claim 1, which requires a conductor/insulator stack as seen in Figs. 23/24. Layer 142 will be etched and removed to form the conducting layer 145 of the stack (paras [0050] – [0057], Fig. 24) and there is no support to show that a part of layer 142 will still be remaining in the second section 166C, after the formation of the conductor/insulator stack, thus introducing new matter and hence rejected.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 26 recites the limitation wherein, “wherein the second section of the GLS structure further includes a third dielectric layer configured between adjacent first dielectric layers, and the third dielectric layer is configured adjacent to a channel hole structure.” It appears that claim 26 is directed to an intermediate step (Fig. 9A), while claim 1, from which claim 26 depends on, is a final product. It is unclear if the claim is directed to an intermediate step or the final device. Hence, the claim is indefinite and therefore rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-11, 14, 21-22 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sim et al. (US 2022/0045083 A1, of record).
Re Claim 1, Sim teaches a three-dimensional (3D) memory device, comprising:
a conductor/insulator stack (ST_G, Figs. 1-2B, paras [0036] – [0037]) including a conductive layer (46g, Fig. 2A, para [0038]) and a first dielectric layer (43, Fig. 2A, para [0037]) alternatingly stacked (see Fig. 2A);
a memory cell region of memory cells (MCA, Fig. 1, para [0036]) in the conductor/insulator stack (ST_G); and
a gate line slit (GLS) structure (82+80+ST_Ia+ST_Ib, Fig. 1, paras [0036] – [0037] and [0051] – [0052]) including a first section (marked “1st section, 82b+80”, in annotated Fig. 1 below), a second section (marked “2nd section, ST_Ib”, in annotated Fig. 1 below), and a third section (marked “3rd section, 82b+80”, in annotated Fig. 1 below) extending along a first direction (x-axis, Fig. 1) from the memory cell region (MCA) to a staircase contact region (SA region, Fig. 1, para [0033]) for separating the memory cells into memory blocks (marked “memory blocks” in annotated Fig. 1 below), wherein
the first section (marked “1st section, 82b+80”, in annotated Fig. 1 below) is adjacent to the memory cell region (MCA), the third section (marked “3rd section, 82b+80”, in annotated Fig. 1 below) is adjacent to the staircase contact region (SA), and the second section (marked “2nd section, ST_Ib”, in annotated Fig. 1 below) is between the first and third sections along the first direction (see annotated Fig. 1 below),
the second section (marked “2nd section, ST_Ib”, in annotated Fig. 1 below) includes the first dielectric layer (43, see Fig. 2B) and a second dielectric layer (46i_2, Fig. 2B, paras [0036] – [0037] and [0043]) that are alternatingly stacked, and
the second dielectric layer (46i_2, Fig. 2B) is in contact with the first and third sections along the first direction, respectively (46i_2 contacts layer 80 of 1st and 3rd sections respectively, see and compare Figs. 1 and 2B).
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Re Claim 2, Sim teaches the 3D memory device according to claim 1, wherein a length of the second section (“2nd section, ST_Ib”) is substantially shorter (see annotated Fig. 1 above) than a length of the first section (“1st section, 82b+80”) along the first direction (x-axis), or the length of the second section (“2nd section, ST_Ib”) is shorter (see annotated Fig. 1 above) than the length of the first section (“1st section, 82b+80”) and a length of the third section (“3rd section, 82b+80”) along the first direction (x-axis), respectively.
Re Claim 3, Sim teaches the 3D memory device according to claim 1, wherein the third section (“3rd section, 82b+80”) is away from the memory cell region of memory cells (MCA, see annotated Fig. 1 above).
Re Claim 4, Sim teaches the 3D memory device according to claim 1, further comprising:
a staircase contact, SCT (91g, Fig. 2B, para [0061]) formed in the staircase contact region (SA region, Figs. 1 and 2B, para [0033]) and adjacent to the third section (“3rd section, 82b+80”), the SCT (91g, Fig. 2B) electrically connected with the memory cell region of memory cells (MCA) by a layer of an electrically conductive material (86g, Fig. 2B para [0061]) adjacent to the second (“2nd section, ST_Ib”) and third sections (“3rd section, 82b+80”).
Re Claim 5, Sim teaches the 3D memory device according to claim 1, wherein a width of the second section (marked “w2”, in annotated Fig. 1 above) is larger than a width of the first section (marked “w1”, in annotated Fig. 1 above) and a width of the third section (marked “w3”, in annotated Fig. 1 above) along a second direction (y-axis, Fig. 1), respectively, and the second direction being perpendicular to the first direction (x-axis).
Re Claim 7, Sim teaches the 3D memory device according to claim 1, wherein the GLS structure (82+80+ST_Ia+ST_Ib) further includes a fourth section (marked “4th section, ST_Ia”, in annotated Fig. 1 above) adjacent to the first section (“1st section, 82b+80”), the first section is between the second section (“2nd section, ST_Ib”) and the fourth section (“4th section, ST_Ia”) along the first direction (x-axis), and a width of the fourth section (marked “w4”, in annotated Fig. 1 above) is larger than the width of the first section (marked “w1”, in annotated Fig. 1 above) along a second direction (y-axis, Fig. 1).
Re Claim 8, Sim teaches a three-dimensional (3D) memory device, comprising:
a conductor/insulator stack (ST_G, Figs. 1-2B, paras [0036] – [0037]) including a conductive layer (46g, Fig. 2A, para [0038]) and a first dielectric layer (43, Fig. 2A, para [0037]) alternatingly stacked (see Fig. 2A);
a region of memory cells (MCA, Fig. 1, para [0036]) in the conductor/insulator stack (ST_G); and
a gate line slit (GLS) structure (82+80+ST_Ia+ST_Ib, Fig. 1, paras [0036] – [0037] and [0051] – [0052]) extending along a first direction (x-axis, Fig. 1) for separating the memory cells into memory blocks (see Fig. 1, where 82 and ST_Ia divide the memory cell region, MCA, into separate memory blocks, marked “memory blocks” in annotated Fig. 1 above), the GLS structure including a first section (marked “1st section, 82b+80”, in annotated Fig. 1 above) adjacent to the region of memory cells (MCA) and a second section (marked “2nd section, ST_Ib”, in annotated Fig. 1 above) adjacent to and aligned with the first section (“1st section, 82b+80”), a length of the second section (“2nd section, ST_Ib”) being substantially shorter than a length of the first section (“1st section, 82b+80”) along the first direction (x-axis, see annotated Fig. 1 above), wherein
the second section (“2nd section, ST_Ib”) includes the first dielectric layer (43, see Fig. 2B) and a second dielectric layer (46i_2, Fig. 2B, paras [0036] – [0037] and [0043]) that are alternatingly stacked, and
the second dielectric layer (46i_2, Fig. 2B) in the second section is in contact with the first section along the first direction (46i_2 contacts layer 80 of 1st section, see and compare Figs. 1 and 2B).
Re Claim 9, Sim teaches the 3D memory device according to claim 8, wherein the GLS structure further comprises a third section (marked “3rd section, 82b+80”, in annotated Fig. 1 above) adjacent to the second section (“2nd section, ST_Ib”), the second section (“2nd section, ST_Ib”) is between the first (“1st section, 82b+80”) and third sections (“3rd section, 82b+80”), a width of the second section (marked “w2” in annotated Fig. 1 above) is larger than a width of the first section (marked “w1” in annotated Fig. 1 above) and a width of the third section (marked “w3” in annotated Fig. 1 above) along a second direction (y-axis), respectively, and the second direction (y-axis) is perpendicular to the first direction (x-axis).
Re Claim 10, Sim teaches the 3D memory device according to claim 9, wherein the third section (“3rd section, 82b+80”) is away from the region of memory cells (MCA, see annotated Fig. 1 above).
Re Claim 11, Sim teaches the 3D memory device according to claim 9, Further comprising:
a staircase contact, SCT (SA region, Figs. 1 and 2B, para [0033]), adjacent to the third section (“3rd section, 82b+80”), the SCT (SA region) electrically connected with the region of memory cells (MCA) by a layer of an electrically conductive material (86g, Fig. 2B, para [0057]) adjacent to the second (“2nd section, ST_Ib”) and third sections (“3rd section, 82b+80”).
Re Claim 14, Sim teaches the 3D memory device according to claim 8, wherein the GLS structure (82+80+ST_Ia+ST_Ib) further includes a fourth section (marked “4th section, ST_Ia”, in annotated Fig. 1 above) adjacent to the first section (“1st section, 82b+80”), the first section is between the second section (“2nd section, ST_Ib”) and the fourth section (“4th section, ST_Ia”) along the first direction (x-axis), a width of the fourth section (marked “w4”, in annotated Fig. 1 above) is larger than a width of the first section (marked “w1”, in annotated Fig. 1 above) along a second direction (y-axis, Fig. 1), and the second direction is perpendicular to the first direction (x-axis).
Re Claim 21, Sim teaches the 3D memory device according to claim 1, wherein the second section (“2nd section, ST_Ib”) of the GLS structure is disposed near a boundary region (see Fig. 1) between the memory cell region (MCA) and the staircase contact region (SA region).
Re Claim 22, Sim teaches the 3D memory device according to claim 1, wherein the second section is made of a material (“2nd section, ST_Ib”, includes the dielectric layer 46i, which is made of silicon nitride, para [0144]) different than the first and third GLS sections (“1st section, 82b+80” and “3rd section, 82b+80”, include layers 82, which is made of silicon oxide, para [0051]).
Re Claim 24, Sim teaches the 3D memory device according to claim 7, wherein the second (“2nd section, ST_Ib”) and fourth sections (“4th section, ST_Ia”) of the GLS structure are made of a same material having a same structure (both the sections contain the insulating dielectric layer 46i, having the same structure, compare Figs. 2A and 2B, paras [0036] – [0037]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Sim et al. (US 2022/0045083 A1, of record).
Re Claim 23, Sim teaches the 3D memory device according to claim 5, but does not explicitly disclose that the width of the second section (marked “w2”, in annotated Fig. 1 above) is at least 20%-50% larger than the width of the first section (marked “w1”, in annotated Fig. 1 above) or the width of the third section (marked “w3”, in annotated Fig. 1 above) along the second direction (y-axis, Fig. 1).
However, looking at annotated Fig. 1 above, it would have been obvious to one of ordinary skill in the art, at the time of invention to realize that the width “w2” is at least 20% larger than the width “w1” or “w3”, within the claimed range.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898