DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nowak et al, US Patent 6,794,718 in view of Yu et al, US Patent Application Publication 2021/0104611 (Both newly submitted)
Regarding claim 1, Nowak teaches an integrated circuit structure, comprising a plurality of fins 40N or 40P, individual ones of the plurality of fins having a longest dimension along a first direction; and a plurality of gate structures 60 over the plurality of fins, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction (figure 6).
Nowak fails to teach a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction, wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of fins and with two or more of the plurality of gate structures in a plan view perspective.
However, Yu teaches the use of connecting wires, which are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device. Figures 2-3 of Yu shows a plurality of lowest metallization lines CW1(M1), IW(M1) along a third direction (Y), the third direction orthogonal to the second direction (X, which is the direction of the gate electrode), wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of fins F1 (as shown in figure 3) and with two or more of the plurality of gate structures in a plan view perspective (shown in figure 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu with that of Nowak because connecting wires are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device.
Regarding claim 2-3, Nowak teaches an angle between the first direction and the second direction is between 30 and 60 degrees and an angle between the first direction and the second direction is between 40 and 50 degrees (45 degrees, see column 4, lines 49-50).
Regarding claim 6, Nowak teaches an integrated circuit structure, comprising a plurality of nanowire stacks 40N or 40P, individual ones of the plurality of nanowire stacks having a longest dimension along a first direction; and a plurality of gate structures over the plurality of nanowire stacks 60, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction (figure 6).
Nowak fails to teach a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction, wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of nanowire stacks and with two or more of the plurality of gate structures in a plan view perspective.
However, Yu teaches the use of connecting wires, which are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device. Figures 2-3 of Yu shows a plurality of lowest metallization CW1(M1), IW(M1) lines along a third direction, the third direction orthogonal to the second direction (X, which is the direction of the gate electrode), wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of nanowire stacks F1 (as shown in figure 3and with two or more of the plurality of gate structures in a plan view perspective (shown in figure 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu with that of Nowak because connecting wires are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device.
Regarding claims 7-8, Nowak teaches an angle between the first direction and the second direction is between 30 and 60 degrees and an angle between the first direction and the second direction is between 40 and 50 degrees (45 degrees, see column 4, lines 49-50).
Claim(s) 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nowak and Yu as applied to claims 1 and 6 above, and further in view of Doornbos, US Patent 10,950,546 (as cited in previous Office Action)
Regarding claims 5 and 10, Nowak and Yu fail to teach a backside power delivery structure beneath the plurality of fins or nanowire stacks.
Doornbos teaches a backside power delivery structure beneath the plurality of fins or nanowire stacks (as referred to in the abstract), in which the backside power delivery circuit includes a first back side power supply wiring coupled to a first potential and a second back side power supply wiring coupled to a second potential different from the first potential.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Doornbos with that of Nowak and Yu because backside power delivery circuits are one type of circuits used in semiconductor devices to minimize power consumption of the semiconductor device, thereby improving the output of the semiconductor device.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nowak et al, US Patent 6,794,718 (newly submitted) in view of Kachian et al, US Patent Application Publication 2014/0091279 (as cited in previous Office Action) and Yu et al, US Patent Application Publication 2021/0104611 (newly submitted)
Regarding claim 11, Nowak teaches a computing device, comprising a component, the component including an integrated circuit structure, comprising a plurality of fins 40N or 40P, individual ones of the plurality of fins having a longest dimension along a first direction and a plurality of gate structures 60 over the plurality of fins, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction (figure 6).
Nowak fails to teach a board; wherein the component is connected to a board, and a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction, wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of fins and with two or more of the plurality of gate structures in a plan view perspective.
However, Kachian teaches a board 702, wherein the components is coupled to the board (figure 7 and [0061]) by teaching a completed semiconductor component, which includes a board, in which components 704, DRAM, 706, which allows for the electrical device to function properly.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kachian with that of Nowak because a motherboard is part of a completed semiconductor components to allow the electrical device to function properly.
Nowak and Kachian fails to teach a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction, wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of fins and with two or more of the plurality of gate structures in a plan view perspective.
However, Yu teaches the use of connecting wires, which are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device. Figures 2-3 of Yu shows a plurality of lowest metallization lines CW1(M1), IW(M1) along a third direction, the third direction orthogonal to the second direction (X, which is the direction of the gate electrode), wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of fins F1 (as shown in figure 3) and with two or more of the plurality of gate structures in a plan view perspective (shown in figure 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu with that of Nowak and Kachian because connecting wires are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device.
Regarding claims 12-15, Kachian teaches a memory DRAM coupled to the board, a communication chip 706 coupled to the board, wherein the component is a packaged integrated circuit die [0061], wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (figure 10 and [0061]).
Regarding claim 16, Nowak teaches a computing device, comprising:
a component, the component including an integrated circuit structure, comprising: a plurality of nanowire stacks 40N or 40P, individual ones of the plurality of nanowire stacks having a longest dimension along a first direction; a plurality of gate structures 60 over the plurality of nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction (figure 6).
Nowak fails to teach a board; wherein the component is connected to a board, and a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction, wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of nanowire stacks and with two or more of the plurality of gate structures in a plan view perspective.
However, Kachian teaches a board 702, wherein the components is coupled to the board (figure 7 and [0061]) by teaching a completed semiconductor component, which includes a board, in which components 704, DRAM, 706, which allows for the electrical device to function properly.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kachian with that of Nowak because a motherboard is part of a completed semiconductor components to allow the electrical device to function properly.
Nowak and Kachian fails to teach a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction, wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of nanowire stacks and with two or more of the plurality of gate structures in a plan view perspective.
However, Yu teaches the use of connecting wires, which are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device. Figures 2-3 of Yu shows a plurality of lowest metallization lines CW1(M1), IW(M1) along a third direction, the third direction orthogonal to the second direction (X, which is the direction of the gate electrode), wherein an individual one of the plurality of lowest metallization lines is overlapping with two or more of the plurality of nanowire stacks F1 (as shown in figure 3) and with two or more of the plurality of gate structures in a plan view perspective (shown in figure 2-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu with that of Nowak and Kachian because connecting wires are generally used in the art to connect the transistors together to allow for electrical flow, which powers the electronic device.
Regarding claims 17-20, Kachian teaches a memory DRAM coupled to the board, a communication chip 706 coupled to the board, wherein the component is a packaged integrated circuit die [0061], wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (figure 10 and [0061]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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