DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yagishita, US Patent Application Publication 2007/0045736.
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Regarding claim 1, Yagishita teaches an integrated circuit structure, comprising: a plurality of fins 13, individual ones of the plurality of fins having a longest dimension along a first direction (as shown in figure above); and a plurality of gate structures over the plurality of fins, individual ones of the plurality of gate structures 11 having a longest dimension along a second direction (as shown in figure above, with the other gate structures being on other structures of the semiconductor devices that are not shown), wherein the first direction is non-orthogonal to the second direction (figure 1 and [0045], which teaches that the fins are inclined between gate electrodes at a 45 degree angle).
Regarding claims 2 and 3, Yagishita teaches an angle between the first direction and the second direction is between 30 and 60 degrees and an angle between the first direction and the second direction is between 40 and 50 degrees [0045].
Regarding claim 4, Yagishita teaches a plurality of lowest metallization lines 20 along a third direction, the third direction orthogonal to the second direction (as shown in figure above).
Regarding claim 6, Yagishita teaches an integrated circuit structure, comprising: a plurality of nanowire stacks 13, individual ones of the plurality of nanowire stacks having a longest dimension along a first direction (as shown in figure above) and a plurality of gate structures 11 over the plurality of nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction (as shown in figure above, with the other gate structures being on other structures of the semiconductor devices that are not shown), wherein the first direction is non-orthogonal to the second direction (figure 1 and [0045], which teaches that the fins are inclined between gate electrodes at a 45 degree angle).
Regarding claims 7 and 8, Yagishita teaches an angle between the first direction and the second direction is between 30 and 60 degrees and an angle between the first direction and the second direction is between 40 and 50 degrees [0045].
Regarding claim 9, Yagishita teaches a plurality of lowest metallization lines along a third direction, the third direction orthogonal to the second direction (as shown in figure above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yagishita as applied to claim 1 above, and further in view of Doornbos, US Patent 10,950,546
Regarding claims 5 and 10, Yagishita fails to teach a backside power delivery structure beneath the plurality of fins or nanowire stacks.
Doornbos teaches a backside power delivery structure beneath the plurality of fins or nanowire stacks (as referred to in the abstract), in which the backside power delivery circuit includes a first back side power supply wiring coupled to a first potential and a second back side power supply wiring coupled to a second potential different from the first potential.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Doornbos with that of Yagishita because backside power delivery circuits are one type of circuits used in semiconductor devices to minimize power consumption of the semiconductor device, thereby improving the output of the semiconductor device.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yagishita, US Patent Application Publication 2007/0045736 in view of Kachian et al, US Patent Application Publication 2014/0091279
Regarding claim 11, Yagishita teaches a computing device, comprising of
a component, wherein the component including an integrated circuit structure, comprising:
a plurality of fins 13, individual ones of the plurality of fins having a longest dimension along a first direction (as shown in figure above); and
a plurality of gate structures 11 over the plurality of fins, individual ones of the plurality of gate structures having a longest dimension along a second direction (as shown in figure above, with the other gate structures being on other structures of the semiconductor devices that are not shown), wherein the first direction is non-orthogonal to the second direction (figure 1 and [0045], which teaches that the fins are inclined between gate electrodes at a 45 degree angle).
Yagishita fails to teach a board, wherein the components is coupled to the board.
However, Kachian teaches a board 702, wherein the components is coupled to the board (figure 7 and [0061]) by teaching a completed semiconductor component, which includes a board, in which components 704, DRAM, 706, which allows for the electrical device to function properly.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kachian with that of Yagishita because a motherboard is part of a completed semiconductor components to allow the electrical device to function properly.
Regarding claims 12-15, Kachian teaches a memory DRAM coupled to the board, a communication chip 706 coupled to the board, wherein the component is a packaged integrated circuit die [0061], wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (figure 10 and [0061]).
Regarding claim 16, Yagishita teaches a computing device, comprising:
a component, the component including an integrated circuit structure, comprising:
a plurality of nanowire stacks 13, individual ones of the plurality of nanowire stacks having a longest dimension along a first direction (as shown in figure above); and
a plurality of gate structures 11 over the plurality of nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction (as shown in figure above, with the other gate structures being on other structures of the semiconductor devices that are not shown, wherein the first direction is non-orthogonal to the second direction (figure 1 and [0045], which teaches that the fins are inclined between gate electrodes at a 45 degree angle).
Yagishita fails to teach a board, wherein the components is coupled to the board.
However, Kachian teaches a board 702, wherein the components is coupled to the board (figure 7 and [0061]) by teaching a completed semiconductor component, which includes a board, in which components 704, DRAM, 706, which allows for the electrical device to function properly.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kachian with that of Yagishita because a motherboard is part of a completed semiconductor components to allow the electrical device to function properly.
Regarding claims 17-20, Kachian teaches a memory DRAM coupled to the board, a communication chip 706 coupled to the board, wherein the component is a packaged integrated circuit die [0061],, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (figure 10 and [0061]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al, US Patent Application Publication 2007/0020855, discloses a FinFET with slanted gate electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899