DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 -2, 5-7, and 10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hung et al. (US 2022/0231010) . Regarding claim 1, Hung et al. discloses, as shown in Figure s 3 A- 6C , an integrated circuit structure comprising: a device layer (309, [0029]) having a front side opposite a backside; a front side metallization layer (307) above the front side of the device layer; a silicon substrate (303) above the front side metallization layer, the silicon substrate having a diode ([0032] -[ 0033]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (315) below the backside of the device layer . Regarding claim 2, Hung et al. discloses the structure further comprising a second backside metallization layer below the backside metallization layer (multiple layers in 315, Figure 3A) . Regarding claim 5, Hung et al. discloses the diode is included in an electrostatic discharge (ESD) circuit [0027] . Regarding claim 6 , Hung et al. discloses, as shown in Figures 3A- 6C , an integrated circuit structure comprising: a device layer (309, [0029]) having a front side opposite a backside; a front side metallization layer (307) above the front side of the device layer; a silicon substrate (303) above the front side metallization layer, the silicon substrate having a bipolar junction transistor therein [0025]) , the bipolar junction transistor coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (315) below the backside of the device layer . Regarding claim 7, Hung et al. discloses the structure further comprising a second backside metallization layer below the backside metallization layer (multiple layers in 315, Figure 3A) . Regarding claim 10, Hung et al. discloses the bipolar junction transistor is included in an electrostatic discharge (ESD) circuit [0027] . Claim(s) 1-2, 5-7, and 10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hung et al. (US 2021/0366846) . Regarding claim 1, Hung et al. discloses, as shown in Figures 2A-5B, an integrated circuit structure comprising: a device layer ( 201, [0017 ]) having a front side opposite a backside; a front side metallization layer ( 2 07 ,209,211 ) above the front side of the device layer; a silicon substrate (30 1, [0025] ) above the front side metallization layer, the silicon substrate having a diode ( 302,304, [ 00 26 ] -[0027] , [0029] ) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (5 01 ) below the backside of the device layer . Regarding claim 2, Hung et al. discloses the structure further comprising a second backside metallization layer below the backside metallization layer ([0039], one or more metallization layers 501) . Regarding claim 5, Hung et al. discloses the diode is included in an electrostatic discharge (ESD) circuit ([0026] -[ 0027] , [0029] ) . Regarding claim 6, Hung et al. discloses, as shown in Figures 2A-5C, an integrated circuit structure comprising: a device layer (201, [0017]) having a front side opposite a backside; a front side metallization layer (207,209,211) above the front side of the device layer; a silicon substrate (301, [0025]) above the front side metallization layer, the silicon substrate having a bipolar junction transistor ([0026] -[ 0027], [0029]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (501) below the backside of the device layer . Regarding claim 7, Hung et al. discloses the structure further comprising a second backside metallization layer below the backside metallization layer ([0039], one or more metallization layers 501). Regarding claim 10, Hung et al. discloses the bipolar junction transistor is included in an electrostatic discharge (ESD) circuit ([0026] -[ 0027], [0029]) . Claim(s) 1- 3 and 5 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Mueller et al. (US 2019/0057950) . Regarding claim 1, Mueller et al. discloses, as shown in Figures 2A-4C, an integrated circuit structure comprising: a device layer ( 202,302, 402, [0032]) having a front side opposite a backside; a front side metallization layer ( 204,304, 404) above the front side of the device layer; a silicon substrate ( 211,311,411 ) above the front side metallization layer, the silicon substrate having a diode ([0032]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer ( 4 15) below the backside of the device layer . Regarding claim 2, Mueller et al. discloses the structure further comprising a second backside metallization layer (414) below the backside metallization layer (Figure 4C ). Regarding claim 3, Mueller et al. discloses the structure further comprising a package substrate (418) below the second backside metallization layer, the package substrate coupled to the second backside metallization layer by a plurality of interconnects (416) . Regarding claim 5, Mueller et al. discloses the diode is included in an electrostatic discharge (ESD) circuit [002 9 ]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 3-4 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2022/0231010) in view of Chen et al. (US 2022/0310470) . Regarding claim s 3 and 8 , Hung et al. discloses the claimed invention including the structure as explained in the above rejection. Hung et al. further discloses a plurality of interconnects coupled to the second backside metallization layer. Hung et al. does not disclose the structure c omprising a package substrate below the second backside metallization layer , and the package substrate coupled to the second backside metallization layer by the second backside metallization layer. However, Chen et al. discloses a structure comprising a package substrate (200). Note Figures 11-15, 22-23 and 30-33 of Chen et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the structure of Hung et al. comprising a package substrate, such as taught by Chen et al. in order to integrate other components to perform the desired function. Regarding claim s 4 and 9 , Hung et al. discloses the claimed invention including the structure as explained in the above rejection. Hung et al. does not disclose the structure c omprising a package lid on the silicon substrate . However, Chen et al. discloses a package lid (208). Note Figure s 11-15, 22-23 and 30-33 of Chen et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the structure of Hung et al. comprising a lid, such as taught by Chen et al. in order to further protect the components and dissipate the heat away from the components . Claim (s) 3-4 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2021/0366846) in view of Chen et al. (US 2022/0310470) . Regarding claims 3 and 8, Hung et al. discloses the claimed invention including the structure as explained in the above rejection. Hung et al. further discloses a plurality of interconnects coupled to the second backside metallization layer. Hung et al. does not disclose the structure c omprising a package substrate below the second backside metallization layer , and the package substrate coupled to the second backside metallization layer by the second backside metallization layer. However, Chen et al. discloses a structure comprising a package substrate (200). Note Figures 11-15, 22-23 and 30-33 of Chen et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the structure of Hung et al. comprising a package substrate, such as taught by Chen et al. in order to integrate other components to perform the desired function. Regarding claims 4 and 9, Hung et al. discloses the claimed invention including the structure as explained in the above rejection. Hung et al. does not disclose the structure c omprising a package lid on the silicon substrate . However, Chen et al. discloses a package lid (208). Note Figures 11-15, 22-23 and 30-33 of Chen et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the structure of Hung et al. comprising a lid, such as taught by Chen et al. in order to further protect the components and dissipate the heat away from the components. Claim (s) 11 -20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2022/0231010) in view of Lee et al. (US 2016/0155686) . Regarding claim 11, Hung et al. discloses, as shown in Figures 3A-3B, a computing device comprising: a component (301) including an integrated circuit structure comprising : a device layer (309, [0029]) having a front side opposite a backside; a front side metallization layer (307) above the front side of the device layer; a silicon substrate (303) above the front side metallization layer, the silicon substrate having a diode ( 302,304, [ 0032]-[0033]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (315) below the backside of the device layer . Hung et al. does not disclose the component coupled to the board. However, Lee et al. discloses a computing device comprising a component coupled to a board (body 2310 may include a system board or mother board) . Note Figures 10C-10D and [0133] -[ 0134] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to couple the component of Hung et al. to the board, such as taught by Lee et al. in order to integrate a plurality of components into the board to perform the desired function. Regarding claim s 12 and 17 , Hung et al. and Lee et al. disclose the device further comprising a memory coupled to the board [0133] -[ 0134] . Regarding claim s 13 and 18 , Hung et al. and Lee et al. disclose the device further comprising a communication chip coupled to the board [0133] -[ 0134] . Regarding claim s 14 and 19 , Hung et al. and Lee et al. disclose the component is a packaged integrated circuit die [0133] -[ 0134] . Regarding claim s 15 and 20 , Hung et al. and Lee et al. disclose the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor [0133] -[ 0134] . Regarding claim 16, Hung et al. discloses, as shown in Figures 3A-3B, a computing device comprising: a component (301) including an integrated circuit structure comprising : a device layer (309, [0029]) having a front side opposite a backside; a front side metallization layer (307) above the front side of the device layer; a silicon substrate (303) above the front side metallization layer, the silicon substrate having a bipolar junction transistor therein [0025]) , the bipolar junction transistor coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (315) below the backside of the device layer . Hung et al. does not disclose the component coupled to the board. However, Lee et al. discloses a computing device comprising a component coupled to a board (body 2310 may include a system board or mother board) . Note Figures 10C-10D and [0133] -[ 0134] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to couple the component of Hung et al. to the board, such as taught by Lee et al. in order to integrate a plurality of components into the board to perform the desired function. Claim (s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2021/0366846) in view of Lee et al. (US 2016/0155686) . Regarding claim 11, Hung et al. discloses, as shown in Figures 2A-5B, a computing device comprising: a component ( 200 ) including an integrated circuit structure comprising : a device layer (201, [0017]) having a front side opposite a backside; a front side metallization layer (207,209,211) above the front side of the device layer; a silicon substrate (301, [0025]) above the front side metallization layer, the silicon substrate having a diode ([0026] -[ 0027], [0029]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (501) below the backside of the device layer . Hung et al. does not disclose the component coupled to the board. However, Lee et al. discloses a computing device comprising a component coupled to a board (body 2310 may include a system board or mother board). Note Figures 10C-10D and [0133] -[ 0134] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to couple the component of Hung et al. to the board, such as taught by Lee et al. in order to integrate a plurality of components into the board to perform the desired function. Regarding claims 12 and 17, Hung et al. and Lee et al. disclose the device further comprising a memory coupled to the board [0133] -[ 0134]. Regarding claims 13 and 18, Hung et al. and Lee et al. disclose the device further comprising a communication chip coupled to the board [0133] -[ 0134]. Regarding claims 14 and 19, Hung et al. and Lee et al. disclose the component is a packaged integrated circuit die [0133] -[ 0134]. Regarding claims 15 and 20, Hung et al. and Lee et al. disclose the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor [0133] -[ 0134]. Regarding claim 16, Hung et al. discloses, as shown in Figures 2 A- 5 B, a computing device comprising: a component ( 200 ) including an integrated circuit structure comprising : a device layer (201, [0017]) having a front side opposite a backside; a front side metallization layer (207,209,211) above the front side of the device layer; a silicon substrate (301, [0025]) above the front side metallization layer, the silicon substrate having a bipolar junction transistor ([0026] -[ 0027], [0029]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (501) below the backside of the device layer . Hung et al. does not disclose the component coupled to the board. However, Lee et al. discloses a computing device comprising a component coupled to a board (body 2310 may include a system board or mother board). Note Figures 10C-10D and [0133] -[ 0134] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to couple the component of Hung et al. to the board, such as taught by Lee et al. in order to integrate a plurality of components into the board to perform the desired function. Claim (s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al. (US 2019/0057950) in view of Chen et al. (US 2022/0310470) . Regarding claim 4, Mueller et al. discloses the claimed invention including the structure as explained in the above rejection. Mueller et al. does not disclose the structure c omprising a package lid on the silicon substrate . However, Chen et al. discloses a package lid (208). Note Figures 11-15, 22-23 and 30-33 of Chen et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the structure of Mueller et al. comprising a lid, such as taught by Chen et al. in order to further protect the components and dissipate the heat away from the components. Claim (s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al. (US 2019/0057950) in view of Lee et al. (US 2016/0155686) . Regarding claim 11, Mueller et al. discloses, as shown in Figures 2A-7, a computing device comprising: a component including an integrated circuit structure comprising : a device layer (202,302,402, [0032]) having a front side opposite a backside; a front side metallization layer (204,304,404) above the front side of the device layer; a silicon substrate (211,311,411) above the front side metallization layer, the silicon substrate having a diode ([0032]) therein, the diode coupled to the device layer through the front side metallization layer by one or more conductive structures; and a backside metallization layer (415) below the backside of the device layer Mueller et al. does not disclose the component coupled to the board. However, Lee et al. discloses a computing device comprising a component coupled to a board (body 2310 may include a system board or mother board). Note Figures 10C-10D and [0133] -[ 0134] of Lee et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to couple the component of Mueller et al. to the board, such as taught by Lee et al. in order to integrate a plurality of components into the board to perform the desired function. Regarding claim 12, Mueller et al. and Lee et al. disclose the device further comprising a memory coupled to the board ([0077], [0079], [0085] of Mueller et al., [0133] -[ 0134] of Lee et al.) Regarding claim 13, Mueller et al. and Lee et al. disclose the device further comprising a communication chip coupled to the board ([0077], [0079], [0085] of Mueller et al., [0133] -[ 0134] of Lee et al.) Regarding claim 14, Mueller et al. and Lee et al. disclose the component is a packaged integrated circuit die [ ([0077], [0079], [0085] of Mueller et al., [0133] -[ 0134] of Lee et al.) Regarding claim 15, Hung et al. and Lee et al. disclose the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor ([0077], [0079], [0085] of Mueller et al., [0133] -[ 0134] of Lee et al.) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT HUNG K VU whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1666 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday: 7am - 5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897