Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/23/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-12 and 21, 22-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hopkins (Pub. No.: US 2024/0203496) (hereinafter `496) in view of Wells (Pub. No.: US 2023/0118763).
Re claim 1, Hopkins teaches a semiconductor device. comprising:
number of decks (three decks) that are stacked up in a Z direction and extend in parallel with an X-Y plane, N being an integer greater than 1, the X-Y plane being perpendicular to the Z direction and having an X direction and a Y direction perpendicular to the X direction, each deck including alternating word line layers (106, FIG. 23, ¶ [0043]) and insulating layers (104), the N number of decks including a first deck and a second deck adjacent to the first deck;
channel structures (“The channel material 2350 of the channel pillar 2348 extends through all decks of the stack 102”, [0098]) each crossing the word line layers (“the word line tiers 106”, [0104]) and the insulating layers (104, [0043]) of the N number of decks; and
a multi-deck gate line slit (GLS) structure (2320/2348/2350, FIGS. 23-24, [0098]) extending in an X-plane and cutting through the word line layers and the insulating layers of the N number of decks, wherein
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the multi-deck GLS structure has a first sidewall in the first deck [FD], a second sidewall in the second deck [SD], and a third side wall ([TSW], FIG. 23 [as shown above]) at a border between the first deck and the second deck, the third sidewall connecting the first sidewall and the second sidewall, and
the second deck (110) is on top of the first deck (108) and the second sidewall [SSW] is less steep than the first sidewall [FSW], or
the second deck is on top of the first deck, and a second segment of the multi-deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment of the multi-deck GLS structure in the first deck.
Hopkins fails to teach the Z direction.
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Wells teaches the Z direction ([ZD], FIG. 14A/14 [as shown above]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of showing the 3D structure in detail as taught by Wells, [0007].
Re claim 2, Hopkins teaches the semiconductor device of claim 1, wherein the second deck [SD] is on top of the first deck [FD], and a lower edge of the second sidewall and an upper edge of the first sidewall are staggered along the Y direction.
Re claim 3, Hopkins teaches the semiconductor of device claim 2. wherein the third sidewall extends in parallel with X-Y plane (right next to the edge).
Re claim 5, Hopkins, FIG. 23 teaches the semiconductor device of claim 1, wherein the multi-deck GLS structure includes N number of per-deck GLS structures (three decks) that correspond to the N number of decks, respectively, and are stacked in the Z direction,
two neighboring per-deck GLS structures meet at each border between two neighboring decks among the N number of decks, and
a lower edge of a sidewall of an upper one [SD] of the two neighboring per-deck GLS structures and an upper edge of a sidewall of a lower one [FD] of the two neighboring per- deck GLS structures are staggered along the Y direction.
Re claim 6, Hopkins, FIG. 23 teaches the semiconductor device of claim 5, wherein a width at a top of the lower one of the two neighboring per-deck GLS structures (W2) is smaller than a width at a bottom of the upper one (width of the area A, note that Applicant did not specify where is the bottom area at) of the two neighboring per-deck GLS structures in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure.
Re claim 7, Hopkins, FIG. 23 teaches the semiconductor device of claim 5, wherein a width at a top of the lower one (W2) of the two neighboring per-deck GLS structures is larger than a width at a bottom of the upper one (width of the area A, note that Applicant did not specify where is the bottom area at) of the two neighboring per-deck GLS structures in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure.
Re claim 8, Hopkins, FIG. 23 teaches the semiconductor device of claim 1, wherein the first sidewall of the multi-deck GLS structure (side wall of 108) passes through multiple decks including the first deck (continuous passing through).
Re claim 9, Hopkins, FIG. 23 teaches the semiconductor device of claim 1, wherein the second deck [SD] is on top of the first deck [FD], and the second sidewall [SSW] is less steep than the first sidewall [FSW].
Re claim 10, Hopkins, FIG. 23 teaches the semiconductor deg ice of claim 1, further comprising:
wherein the channel structures each having a charge trapping layer sandwiched between a blocking layer and a tunneling layer,
wherein at a border of any two neighboring decks among the N number of decks, a sidewall of an upper portion of one of the channel structures in an upper one of the two neighboring decks [SD] and a sidewall of a lower portion of the one of the channel structures in a lower one [FD] of the two neighboring decks are staggered [TSW].
Re claim 11, Hopkins, FIG. 23 teaches the semiconductor device of claim 10, wherein, for each of the N number of decks except the last deck, portions of the channel structures in the deck and a portion of the multi-deck GLS structure in the deck are formed during a same etch process [0008].
Re claim 12, Hopkins, FIG. 23 teaches the semiconductor device of claim1, further comprising a contact region where word line contacts are positioned, wherein
one of the word line contacts that corresponds to a respective word line layer (by looking down to layer 106) among the word line layers included in the N number of decks extends in the Z direction and passes the word line layers included in the N number of decks that are above the respective word line layer.
Re claim 21, Hopkins, FIG. 23 [as shown above] teaches a device of a memory system, comprising:
a controller (2602, FIG. 26);
interface circuitry (2618/2616) for connecting the controller to a host device: and
a memory device connected to the controller, the memory device including:
number of decks that are stacked up in a Z direction and extend in parallel with an X-Y plane, N being an integer greater than 1, the X-Y plane being perpendicular to the Z direction and having an X direction and a Y direction perpendicular to the X direction, each deck including alternating word line layers (106) and insulating layers (104), the N number of decks including a first deck and a second deck adjacent to the first deck;
channel structures (“The channel material 2350 of the channel pillar 2348 extends through all decks of the stack 102”, [0098]) each crossing the word line layers (“the word line tiers 106”, [0104]) and the insulating layers (104, [0043]) of the N number of decks; and
a multi-deck gate line slit (GLS) structure (2320/2348/2250, FIGS. 23-24) extending in an X-Z plane and cutting through the word line layers and the insulating layers of the N number of decks, wherein
the multi-deck CLS structure has a first sidewall in the first deck [FD], a second sidewall in the second deck [SD], and a third sidewall [TSW] at a border between the first deck and the second deck, the third sidewall connecting the first sidewall [FSW] and the second sidewall [SSW], and
the second deck (110) is on top of the first deck (108) and the second sidewall [SSW] is less steep than the first sidewall [FSW], or
the second deck is on top of the first deck, and a second segment of the multi-deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment of the multi-deck GLS structure in the first deck.
Hopkins fails to teach the Z direction.
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Wells teaches the Z direction ([ZD], FIG. 14A/14 [as shown above]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of showing the 3D structure in detail as taught by Wells, [0007].
Re claim 22/23, Hopkins, FIG. 23 [as shown above] teaches the semiconductor device of claim 1, wherein the second deck [SD] is on top of the first deck [FD], and a second segment (W1) of the multi-deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment (W2) of the multi-deck GLS structure in the first deck.
Re claim 24, Hopkins, FIG. 23 [as shown above] teaches the device of claim 21, wherein the second deck [SD] is on top of the first deck [FD] and the second sidewall [SSW] is less steep that the first sidewall [FSW].
Re claim 25, Hopkins, FIGS. 1/23-24 teaches the device of claim 21, further comprising:
wherein the channel structures each having a charge trapping layer sandwiched between a blocking layer and a tunneling layer [0047], wherein, at a border of any two neighboring decks among the N number of decks, a sidewall of an upper portion of one of the channel structures in an upper one of the two neighboring decks and a sidewall of a lower portion of the one of the channel structures in a lower one of the two neighboring decks are staggered (124/126, [0049]).
Re claim 26, Hopkins, FIG. 23 [as shown above] teaches the device of claim 25. wherein, for each of the N number of decks except the last deck, portions of the channel structures in the deck and a portion of the multi-deck OLS structure in the deck are formed during a same etch process [0100].
Re claim 27, Hopkins, FIG. 23 [as shown above] teaches the device of claim 21, wherein the second deck is on top of the first deck, and a lower edge of the second sidewall [SSW] and an upper edge of the first sidewall [FSW] are staggered along the Y direction.
Claim(s) 1-3 and 5-12, 21, 22-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wells in view of another Hopkins (Pub. No.: US 2024/0203496) (hereinafter `496).
Re claim 1, Wells teaches a semiconductor device. comprising:
N number of decks (two decks) that are stacked up in a Z direction and extend in parallel with an X-Y plane, N being an integer greater than 1, the X-Y plane being perpendicular to the Z direction and having an X direction and a Y direction perpendicular to the X direction, each deck including alternating word line layers (16/40, FIG. 14, ¶ [0068]) and insulating layers (18/42), the N number of decks including a first deck and a second deck adjacent to the first deck;
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channel structures (68, [0055]) each crossing the word line layers (16/40) and the insulating layers (18/42) of the N number of decks along the Z direction ([ZD], FIG. 14A/14 [as shown above]), and
a multi-deck gate line slit (GLS) structure (70/72/76/78/80, FIG. 11A, [0058]-[0063]) extending in an X-plane and cutting through the word line layers and the insulating layers of the N number of decks, wherein
the multi-deck GLS structure has a first sidewall in the first deck (24/Deck-1), a second sidewall in the second deck (48/Deck-2), and a third side wall (inter-deck region 58, [0045]) at a border between the first deck and the second deck, the third sidewall connecting the first sidewall and the second sidewall.
Wells fails to teach the second deck is on top of the first deck and the second sidewall is less steep than the first sidewall, or
the second deck is on top of the first deck, and a second segment of the multi- deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment of the multi-deck GLS structure in the first deck.
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`496, FIG. 22 [as shown above] teaches the second deck [SD] is on top of the first deck [FD] and the second sidewall [SSW] is less steep than the first sidewall [FSW], or
the second deck is on top of the first deck, and a second segment of the multi-deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment of the multi-deck GLS structure in the first deck.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the manufacturing process as taught by `496, ¶¶ [0002]-[0004].
Re claim 2, in the combination, Wells, FIG. 14 teaches the semiconductor device of claim 1, wherein the second deck (48) is on top of the first deck (24), and a lower edge of the second sidewall and an upper edge of the first sidewall are staggered along the Y direction.
Re claim 3, in the combination, Wells, FIG. 14 teaches the semiconductor of device claim 2, wherein the third sidewall extends in parallel with X-Y plane (right next to the edge).
Re claim 5, in the combination, Wells, FIG. 14 teaches the semiconductor device of claim 1, wherein the multi-deck GLS structure includes N number of per-deck GLS structures (two decks) that correspond to the N number of decks, respectively, and are stacked in the Z direction,
two neighboring per-deck GLS structures meet at each border between two neighboring decks among the N number of decks, and
a lower edge of a sidewall of an upper one (48) of the two neighboring per-deck GLS structures and an upper edge of a sidewall of a lower one (24) of the two neighboring per-deck GLS structures are staggered along the Y direction.
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Re claim 6, in the combination, Wells, FIG. 14 teaches the semiconductor device of claim 5, wherein a width at a top of the lower one of the two neighboring per-deck GLS structures (W1) is smaller than a width at a bottom of the upper one [W2] of the two neighboring per-deck GLS structures in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure.
Re claim 7, in the combination, Wells, FIG. 14 teaches the semiconductor device of claim 5, wherein a width at a top of the lower one [W2] of the two neighboring per-deck GLS structures is larger than a width at a bottom of the upper one ([W1], note that Applicant did not specify where is the bottom area at) of the two neighboring per-deck GLS structures in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure.
Re claim 8, in the combination, Wells, FIG. 11A teaches the semiconductor device of claim 1, wherein the first sidewall of the multi-deck GLS structure (side wall of (70/72/76/78/80) passes through multiple decks including the first deck (continuous passing through).
Re claim 9, in the combination, `496, FIG. 22 [as shown above] teaches the semiconductor device of claim 1, wherein the second deck [SD] is on top of the first deck [FD], and the second sidewall [SSW] is less steep than the first sidewall [FSW].
Re claim 10, in the combination, Wells, FIG. 14 teaches the semiconductor deg ice of claim 1, further comprising:
wherein the channel structures each having a charge trapping layer sandwiched between a blocking layer and a tunneling layer,
wherein, at a border of any two neighboring decks among the N number of decks, a sidewall of an upper portion of one of the channel structures in an upper one of the two neighboring decks (48) and a sidewall of a lower portion of the one of the channel structures in a lower one (48) of the two neighboring decks are staggered (inter-deck area around 58).
Re claim 11, in the combination, Wells, FIG. 13 teaches the semiconductor device of claim 10, wherein, for each of the N number of decks except the last deck, portions of the channel structures in the deck and a portion of the multi-deck GLS structure in the deck are formed during a same etch process [0065].
Re claim 12, in the combination, Wells teaches the semiconductor device of claim1, further comprising a contact region where word line contacts are positioned, wherein
one of the word line contacts that corresponds to a respective word line layer (by looking down to layer (16/40), FIG. 14A) among the word line layers included in the N number of decks extends in the Z direction and passes the word line layers included in the N number of decks that are above the respective word line layer.
Re claim 21, Wells teaches a device of a memory system, comprising:
a controller (1018);
interface circuitry (1007) for connecting the controller to a host device: and
a memory device connected to the controller, the memory device including:
N number of decks that are stacked up in a Z direction and extend in parallel with an X-Y plane, N being an integer greater than 1, the X-Y plane being perpendicular to the Z direction and having an X direction and a Y direction perpendicular to the X direction, each deck including alternating word line layers (16/40, FIG. 14, ¶ [0068]) and insulating layers (18/42), the N number of decks including a first deck and a second deck adjacent to the first deck;
channel structures (68, [0055]) each crossing the word line layers (16/40) and the insulating layers (18/42) of the N number of decks along the Z direction ([ZD], FIG. 14A/14 [as shown above]), and
a multi-deck gate line slit (GLS) structure (70/72/76/78/80, FIG. 11A, [0058]-[0063]) extending in an X-Z plane and cutting through the word line layers and the insulating layers of the N number of decks, wherein
the multi-deck CLS structure has a first sidewall in the first deck (24), a second sidewall in the second deck (48), and a third sidewall (inter-deck region 58, [0045]) at a border between the first deck and the second deck, the third sidewall connecting the first sidewall and the second sidewall.
Wells fails to teach the second deck is on top of the first deck and the second sidewall is less steep than the first sidewall, or
the second deck is on top of the first deck, and a second segment of the multi- deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment of the multi-deck GLS structure in the first deck.
`496, FIG. 22 [as shown above] teaches the second deck [SD] is on top of the first deck [FD] and the second sidewall [SSW] is less steep than the first sidewall [FSW], or
the second deck is on top of the first deck, and a second segment of the multi-deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment of the multi-deck GLS structure in the first deck.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the manufacturing process as taught by Hopkins, [0002]-[0004].
Re claim 22/23, in the combination, Wells teaches the semiconductor device of claim 1, wherein the second deck [SD] is on top of the first deck [FD], and a second segment (W2) of the multi-deck GLS structure in the first deck has a bottom width larger than or equal to a top width of a first segment (W1) of the multi-deck GLS structure in the first deck.
Re claim 24, in the combination, Wells, FIG. 22 [as shown above] teaches the device of claim 21, wherein the second deck [SD] is on top of the first deck [FD] and the second sidewall [SSW] is less steep that the first sidewall [FSW].
Re claim 25, in the combination, Wells, FIG. 11A [as shown above] teaches the device of claim 21, further comprising:
wherein the channel structures each having a charge trapping layer sandwiched between a blocking layer and a tunneling layer [0047],
wherein, at a border of any two neighboring decks among the N number of decks, a sidewall of an upper portion of one of the channel structures in an upper one of the two neighboring decks and a sidewall of a lower portion of the one of the channel structures in a lower one of the two neighboring decks are staggered (inter-deck area around 58, FIG. 9).
Re claim 26, in the combination, Wells, FIG. 11A [as shown above] teaches the device of claim 25. wherein, for each of the N number of decks except the last deck, portions of the channel structures in the deck and a portion of the multi-deck OLS structure in the deck are formed during a same etch process [0065].
Re claim 27, in the combination, `496, FIG. 22 [as shown above] teaches the device of claim 21, wherein the second deck [SD] is on top of the first deck [FD], and a lower edge of the second sidewall [SSW] and an upper edge of the first sidewall [FSW] are staggered along the Y direction.
Re claim 28, in the combination, Wells, FIG. 11A [as shown above] teaches the of device claim 27, wherein the third sidewall extends in parallel with X-Y plane (horizonal plane along the interface of 44 and 22).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hopkins/Wells or Well/`496 in view of another LEE (Pub. No.: US 2024/0188300).
Re claim 4, Hopkins or Wells teaches all the limitation of claim 1.
Hopkins or Well/`496s fails to teach the limitation of claim 4.
LEE teaches wherein, in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure, a profile of the multi-deck GLS structure (214, FIG. 2F, ¶ [0031]) is discontinuous at the border between the first deck and the second deck.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of providing offset for the conduction band and the valence band for the transistor devices of the memory cells as taught by LEE, [0031].
Response to Arguments
Applicant's arguments with respect to claims 1 and 21 on the remarks filed on 04/01/2026 have been considered but they are not persuasive because Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28 F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as “enabled disclosures.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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