Prosecution Insights
Last updated: July 17, 2026
Application No. 18/089,945

TRANSISTOR INCLUDING WIDE BAND GAP MATERIALS

Non-Final OA §103
Filed
Dec 28, 2022
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
505 granted / 813 resolved
-5.9% vs TC avg
Strong +24% interview lift
Without
With
+24.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
57 currently pending
Career history
862
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
82.9%
+42.9% vs TC avg
§102
7.1%
-32.9% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 813 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species A, represented by figures 1A-1B and claims 1-6 in the reply filed on April 2, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Information Disclosure Statement As of April 13, 2026, no information disclosure statement has been made of record. Drawing Objections The drawings are objected to because: Figure 1B contains a plurality of unlabeled elements. These elements are shown below. PNG media_image1.png 524 775 media_image1.png Greyscale Response to arguments dated April 2, 2026 Applicant states they do not need to label the unlabeled elements shown in Examiner’s figure 1. Applicant states this is because these unlabeled elements are not claimed. This argument is unpersuasive. Assuming the unlabled items are conventional they must still be labeled in the drawings. MPEP 608.02(d) citing 37 CFR 1.83(a), where “conventional features disclosed in the description and claims, where their detailed illustration is not essential for a proper understanding of the invention, should be illustrated in the drawing in the form of a graphical drawing symbol or a labeled representation (e.g., a labeled rectangular box).” Based upon the Rules figure 1B continues to be objected to. See MPEP 608.02(e) and form paragraph 6.22.01, where Examiner can object to the drawings because they fail to label, and thereby show, “structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing.” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2018/0012868 A1), in view of Wong et al. (US 2015/0123170 A1) (“Wong”), in view of linking reference Wu et al. (US 2001/0023964 A1) (“Wu”), in view Raring et al. (US 9,666,677 A1) (“Raring”). Regarding claim 1, Huang teaches at least in figure 1-2f: A III-V material (200); a first gate (204) over the III-V material (200); an material (103) beneath the III-V material (200); and a second gate (104) beneath the material (103). Huang does not teach: The III-V material is GaN. a first material on the GaN material, wherein the first material is at a first side of the first gate; a second material on the GaN material, wherein the second material is at a second side of the first gate opposite the first side of the first gate; wherein the body includes a first wide band gap material, and wherein the first material and the second material are doped GaN regions; the material is a SiC material. In regards to the material. Huang teaches the material 103 is an insulating material. However, Huang does not teach the insulating material comprises SiC. Huang teaches the insulating material 103 silicon oxide. ¶ 0013. Wong teaches at least in figure 1: That SICO can replace silicon oxide as an interlayer dielectric material (e.g. they cover transistors), ¶ 0022, as they are art recognized equivalents for the same purpose of being an interlayer dielectric material, MPEP 2144.06, and are art recognized as being suitable for the same intended purpose of being an interlayer dielectric material, MPEP 2144.07. Thus, the substitution of the silicon carbide material, SiCO, for silicon oxide would have been obvious to one of ordinary skill in the art. Huang and Wong do not teach: The III-V material is GaN. a first material on the GaN material, wherein the first material is at a first side of the first gate; a second material on the GaN material, wherein the second material is at a second side of the first gate opposite the first side of the first gate; wherein the body includes a first wide band gap material, and wherein the first material and the second material are doped GaN regions; This is because Huang teaches: The III-V material can be GaAs, InAs, InP, etc. Linking reference Wu teaches: That the wide bandgap III-V material GaN is superior to other III-V materials such as GaAs as a device using GaN can produce ten times the power of GaAs devices. ¶ 0008. Therefore, it would have been obvious to one of ordinary skill in the art to replace the III-V material of Huang with a GaN device in order to obtain this increase in power. Raring teaches such a GaN device in at least in figures 11A, 11g, 11j: The III-V material is GaN (the figures call this GaN). a first material on the GaN material (figure 11g n-GaN source), wherein the first material is at a first side of the first gate (Gate); a second material on the GaN material (figure 11g a second n-GaN drain), wherein the second material is at a second side of the first gate opposite the first side of the first gate (both source and drain are on opposite sides of gate) ; and wherein the first material and the second material are doped GaN regions (both source and drain are doped are indicated by the use of “n-“. Where if they were not doped they would have just been called GaN). As stated above with respect to Wu, it would have been obvious to one of ordinary skill in the art to replace the III-V material of Huang with the III-V GaN material as it would have allowed one to increase the power of the III-V transistors. Regarding claim 3, wherein the first material has a first level of doping concentration and wherein the second material has a second level of doping concentration (it would have been obvious to one of ordinary skill in the art that the source would have a different level of doping than the drain because of standard process variations one would not expect the source and drain to have the exact same, e.g. identical, doping down to the same dopant atom. There will obviously be some doping variation between the source and drain. All the claim requires is one atom of dopant difference. This is obvious). Regarding claim 4, Raring teaches such a GaN device in at least in figures 11A, 11g, 11j: a first electrical contact on the first material; and a second electrical contact on the second material (Col. 50 at lines 30-34, where there are electrical contacts on the source and drain). Regarding claim 5, Huang teaches at least in figure 1-2f: a third electrical contact laterally spaced apart from the second gate (this would be the source or drain region of the transistors 104. Where the third electrical contact could be the source/drain contact connecting to 108). Regarding claim 6, Huang teaches at least in figure 1-2f: wherein the first electrical contact is vertically overlapping with third electrical contact (As can be seen in the figures of Huang there are a plurality of source/drain contacts for transistor 204 which overlap with a plurality of source/drain contacts for transistors 104.). Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang, in view of Wong, in view of linking reference Wu, in view Raring, in view of Koester (US 2005/0104092 A1) (“Koester”). Regarding claim 2, Huang does not teach: The material of the second gate. Raring teaches: The material of the first gate can be Ni/AU, Pt, Pd, Au, etc. Col. 50 at lines 34-37. Koester teaches at least in figure 1(a): That silicon mosfet gates, such as the one of Huang, can be made out of “polysilicon, polysilicon germanium, or the metals: Mo, Pt, Ir, W, Pd, Al, Au, Ni, Cu, Ti…” ¶ 0024. It would have been obvious to one of ordinary skill in the art that the second gate could be made out of the materials described by Koester as they are well-known gate materials to use in the second gate of Huang. Based upon the materials described by Koester and Raring it would have been obvious to one of ordinary skill in the art that the materials of the first gate can be different from the materials of the second gate. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Dec 28, 2022
Application Filed
Aug 01, 2023
Response after Non-Final Action
Mar 09, 2026
Response after Non-Final Action
Mar 23, 2026
Response after Non-Final Action
Apr 24, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+24.5%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 813 resolved cases by this examiner. Grant probability derived from career allowance rate.

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