The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Patent Application Publication 2018/0138092, hereinafter referred to as Lee).
As to claim 1, Lee teaches 1. An integrated circuit comprising: a first device including (i) a first source or drain region, (ii) a first body of semiconductor material extending laterally from the first source or drain region, (iii) a first gate structure on the first body, and (iv) a first contact extending vertically upward from the first source or drain region [see Fig. 1, 3 for example; 150, 320]; a second device including (i) a second source or drain region, (ii) a second body of semiconductor material extending laterally from the second source or drain region, (iii) a second gate structure on the second body, and (iv) a second contact extending vertically upward from the second source or drain region [see Fig. 1, 4 for example; 250, 420]; a gate cut structure comprising dielectric material laterally between the first gate structure and the second gate structure [see Fig. 1, 5 for example; 160], and also laterally between the first contact and the second contact; and a third contact extending laterally from the first contact to the second contact and over the gate cut structure [see Fig. 22 for example; 170, 270, 165].
As to claim 2, Lee teaches 2. The integrated circuit of claim 1, wherein the third contact extends laterally from an upper surface of the first contact to an upper surface of the second contact. [see Fig. 22 for example; 170, 270, 165]
As to claim 3, Lee teaches 3. The integrated circuit of claim 1, further comprising: a third device including (i) a third source or drain region, and (ii) a third body of semiconductor material extending laterally from the third source or drain region, wherein the first gate structure is on the third body, and wherein the first contact extends vertically upward from the third source or drain region. [see Fig. 33 for example]
As to claim 4, Lee teaches 4. The integrated circuit of claim 1, further comprising: a third device including (i) a third source or drain region, (ii) a third body of semiconductor material extending laterally from the third source or drain region, (iii) a third gate structure on the third body, and (iv) a fourth contact extending vertically upward from the third source or drain region; wherein a portion of the first contact, which is on a sidewall of the first source or drain region, has a first width; and wherein a portion of the fourth contact, which is on a sidewall of the third source or drain region, has a second width that is at least 2 nanometers less than the first width. [see Fig. 33 for example]
As to claim 5, Lee teaches 5. The integrated circuit of claim 1, wherein: the first source or drain region has a first sidewall facing the second source or drain region, and a second sidewall that is on an opposite side of the first sidewall; a first portion of the first contact, which is on the first sidewall of the first source or drain region, has a first width; and a second portion of the first contact, which is on the second sidewall of the first source or drain region, has a second width that is at least 2 nanometers less than the first width. [see Fig. 22, 24 for example]
As to claim 6, Lee teaches 6. The integrated circuit of claim 1, wherein the second width is at least 5 nanometers less than the first width. [see Fig. 22, 24 for example]
As to claim 7, Lee teaches 7. The integrated circuit of claim 1, wherein: the first source or drain region has a first sidewall facing the second source or drain region, and a second sidewall that is on an opposite side of the first sidewall; a portion of the first contact is on the first sidewall of the first source or drain region; and no portion of the first contact is on the second sidewall of the first source or drain region. [see Fig. 22, 24 for example]
As to claim 8, Lee teaches 8. The integrated circuit of claim 1, wherein each of the first body and the second body is a nanoribbon, a nanosheet, a nanowire, or a fin. [¶0035]
As to claim 9, Lee teaches 9. The integrated circuit of claim 1, wherein the gate cut structure is also laterally between the first source or drain region and the second source or drain region. [see Fig. 1, 160 for example]
As to claim 10, Lee teaches 10. The integrated circuit of claim 1, wherein the gate cut structure is a continuous structure of the dielectric material that is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact [see Fig. 1, 160 for example]
As to claim 11, Lee teaches 11. The integrated circuit of claim 1, wherein the first contact comprises: conductive fill material; and a conductive liner layer of one or more walls of the first contact. [see Fig. 21, 22 for example]
As to claim 12, Lee teaches 12. The integrated circuit of claim 11, wherein the conductive liner layer is present between the conductive fill material of the first contact and at least a section of the first source or drain region, and the conductive liner layer is absent between the conductive fill material of the first contact and at least a section of the gate cut structure. [see Fig. 21, 22 for example]
As to claim 13, Lee teaches 13. An integrated circuit comprising: a first device including (i) a first source or drain region, (ii) a first gate structure, and (iii) a first contact extending above from the first source or drain region; a second device including (i) a second source or drain region, (ii) a second gate structure, and (ii) a second contact extending above from the second source or drain region; a third device including (i) a third source or drain region, (ii) a third gate structure, and (ii) a third contact extending above from the third source or drain region; and a gate cut comprising dielectric material laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact; wherein a portion of the first contact that is on a sidewall of the first source or drain region has a first width; wherein a portion of the third contact that is on a sidewall of the third source or drain region has a second width; and the first width is greater than the second width by at least 2 nanometers. [see rejection claim 1,5 above]
As to claim 14, Lee teaches 14. The integrated circuit of claim 13, wherein: the portion of the first contact having the first width is a first portion; the sidewall of the first source or drain region, on which the first portion of the first contact having the first width is located, is a first sidewall of the first source or drain region; the first sidewall of the first source or drain region faces the gate cut and the second source or drain region; the first source or drain region has a second sidewall opposite the first sidewall; a second portion of the first contact that is on the second sidewall of the first source or drain region has a third width; and the first width is greater than the third width by at least 2 nanometers. [see rejection claim 1, 5 above]
As to claim 15, Lee teaches 15. The integrated circuit of claim 13, wherein: the sidewall of the first source or drain region, on which the portion of the first contact having the first width is located, is a first sidewall of the first source or drain region; the first sidewall of the first source or drain region faces the gate cut and the second source or drain region; the first source or drain region has a second sidewall opposite the first sidewall; and no portion of the first contact is on the second sidewall of the first source or drain region. [Fig. 21, 22 for example]
As to claim 16, Lee teaches 16. The integrated circuit of claim 13, further comprising: a fourth contact extending laterally from an upper surface of the first contact to an upper surface of the second contact, wherein the fourth contact is above a portion of the gate cut. [Fig. 33 for example]
As to claim 17, Lee teaches 17. An integrated circuit comprising: a first source or drain region, and a first contact that is in contact with top and side surfaces of the first source or drain region; a second source or drain region, and a second contact that is in contact with top and side surfaces of the second source or drain region; and a gate cut structure extending laterally between the first contact and the second contact; and wherein each of the side surface of the first source or drain region and the side surface of the second source or drain region are facing the gate cut structure. [see rejection claim 1 above]
As to claim 18, Lee teaches 18. The integrated circuit of claim 17, further comprising: a conductive structure extending laterally from an upper surface of the first contact to an upper surface of the second contact, the conductive structure extending above the gate cut structure. see rejection claim 4 above]
As to claim 19, Lee teaches 19. The integrated circuit of claim 17, further comprising: a first body of semiconductor material extending laterally from the first source or drain region, and a first gate structure on the first body; a second body of semiconductor material extending laterally from the second source or drain region, and a second gate structure on the second body; wherein the gate cut structure extends laterally between the first gate structure and the second gate structure. [see rejection claim 1 above]
As to claim 20, Lee teaches 20. The integrated circuit of claim 17, wherein: the first source or drain region has a first sidewall facing the second source or drain contact, and an opposing second sidewall; a first portion of the first contact, that is on the first sidewall of the first source or drain region, has a first width; a second portion of the first contact, that is on the second sidewall of the first source or drain region, has a second width; and the first width is greater than the second width by at least 2 nanometers. [see rejection claim 1,5 above]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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