DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species 1, Fig. 1A, claims 1-8, 10-17 and 21-23, in the reply filed on March 19, 2026 is acknowledged. The traversal is on the ground(s) “that there would be no excess examination burden to fully examine all claims”. This is not found persuasive because the Examiner would have to develop search strategies for multiple inventions instead of one. This would require the Examiner search other CPC classes not related to the Applicant’s chosen species. Lastly, the MPEP states that there can be only patent per invention, hence, one invention per application.
The requirement is still deemed proper and is therefore made FINAL. Claims 18-20 have be cancelled by the Applicant. Claim 9 has been withdrawn by the Applicant. Action on the merits is as follows:
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the first source or drain terminal and the second source or drain terminal are each multilayer structures” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, 10-17 and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (Yamazaki) (US 2013/0181214 A1).
In regards to claim 1, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses an integrated circuit structure (Fig. 2C), comprising: a first layer (item 403) comprising a semiconductor material (item 403, paragraphs 101, 104, 106); a second layer (items 402, 407 or 402 plus 407) above the first layer (item 403), the second layer (items 402, 407 or 402 plus 407) comprising a metal and one of oxygen or nitrogen (paragraphs 191, 184, 185, 195, 197), wherein the second layer (items 402, 407 or 402 plus 407) has a thickness of at most 20 nanometers (nm) (paragraph 23); and a first source or drain terminal (items 405a or 405b) and a second source or drain terminal (items 405a or 405b), each of the first and second source or drain terminals (items 405a and 405b) extends through the second layer (items 402, 407 or 402 plus 407) and is landed on the first layer (item 403).
In regards to claim 2, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses wherein the second layer (items 402, 407 or 402 plus 407) is an etch stop layer. Examiner notes that Yamazaki (paragraphs 191, 184, 185, 195, 197) discloses that the second layer (items 402, 407 or 402 plus 407) discloses the same materials (aluminum oxide, an oxide or a nitride) as the Applicant [0045] “the etch stop layer 116 comprise an oxide or a nitride, such as aluminum oxide (Al.sub.2O.sub.3) in an example. For example, the etch stop layer 116 comprising aluminum oxide (or another appropriate oxide or a nitride)”. Therefore the second layer of Yamazaki can share the same characteristics/functionality as an etch stop layer.
In regards to claim 3, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses wherein the second layer (items 402, 407 or 402 plus 407) comprises aluminum and oxygen (paragraphs 191, 184, 185, 195, 197, aluminum oxide).
In regards to claim 4, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses further comprising: a dielectric material (item 415) above the second layer (items 402, 407 or 402 plus 407), wherein the dielectric material (item 415) is elementally and/or compositionally different (paragraph 199, silicon oxynitride, silicon oxide) from the second layer (items 402, 407 or 402 plus 407).
In regards to claim 5, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses wherein the dielectric material (item 415) is etch selective with respect to the second layer (items 402, 407 or 402 plus 407), such that an etch process to etch the dielectric material (item 415) doesn't substantially etch the second layer (items 402, 407 or 402 plus 407).
In regards to claim 7, Yamazaki (Fig. 2C and associated text) discloses further comprising: a gate structure (items 401 plus 402) comprising (i) a gate electrode (item 401) and (ii) a gate dielectric material (item 402) that separates the first layer (item 403) from the gate electrode (item 401).
In regards to claim 8, Yamazaki (Fig. 2C and associated text) discloses wherein the first layer (item 403) is above the gate structure (items 401 plus 402).
In regards to claim 10, Yamazaki (Fig. 2C and associated text) discloses wherein the first layer (item 403) has a thickness in a range of 5-25 nm (paragraph 251), and wherein the thicknesses of the first layer (item 403) and the second layer (items 402, 407 or 402 plus 407) are measured in a direction perpendicular to a length of the first layer (item 403).
In regards to claim 11, Yamazaki (Fig. 2C and associated text) discloses wherein the integrated circuit structure (Fig. 2C) is a thin film transistor (TFT) structure (item 440d), with the first layer (item 403) being a thin film oxide semiconductor layer (item 403, paragraphs 101, 104, 106) of the TFT (item 440d).
In regards to claim 12, Yamazaki (Fig. 2C and associated text) discloses wherein the semiconductor material of the first layer (item 403) comprises an oxide semiconductor material (paragraphs 101, 104, 106).
In regards to claim 13, Yamazaki (Fig. 2C and associated text) discloses wherein the first source or drain terminal (items 405a or 405b) and the second source or drain terminal (items 405a or 405b) are each multilayer structures. Examiner takes official notice that it is well known in the art that conductive/metal structures/contacts/terminals can be single or multi-layered structures.
In regards to claim 14, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses thin film transistor (TFT) structure (items 440a, 440c, 440d), comprising: a layer comprising a metal and oxygen (item 403, paragraphs 101, 104, 106); an etch stop layer on the layer comprising the metal and oxygen (items 402, 407 or 402 plus 407); a dielectric material (item 415) above the etch stop layer (items 402, 407 or 402 plus 407); and a source terminal and a drain terminal (items 405a and 405b), each of the source and drain terminals (items 405a and 405b) extending through the dielectric material (item 415) and the etch stop layer (items 402, 407 or 402 plus 407) and in contact with the layer comprising the metal and oxygen (item 403, paragraphs 101, 104, 106).
In regards to claim 15, Yamazaki (Fig. 2C and associated text) discloses further comprising: a gate electrode (item 401) below the layer comprising the metal and oxygen (item 403); and a gate dielectric material (item 402) between the gate electrode (item 401) and the layer comprising the metal and oxygen (item 403).
In regards to claim 16, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses wherein the etch stop layer (items 402, 407 or 402 plus 407) is etch selective to the dielectric material (item 415), such that an etch process through the dielectric material (item 415) doesn't substantially etch the etch stop layer (items 402, 407 or 402 plus 407).
In regards to claim 17, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses wherein the etch stop layer (items 402, 407 or 402 plus 407) comprises aluminum and oxygen (paragraphs 191, 184, 185, 195, 197).
In regards to claim 21, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses a thin film transistor (TFT) structure (item 440d), comprising: a first layer comprising a first metal and oxygen (item 403, paragraphs 101, 104, 106); a second layer (items 402, 407 or 402 plus 407) directly on the first layer (item 403) and comprising a second metal (aluminum), and oxygen (paragraphs 191, 184, 185, 195, 197), the second metal (aluminum)being different from the first metal (paragraph 106, tin zinc, Hf, etc.); a dielectric material (item 415) above the second layer (items 402, 407 or 402 plus 407); and a source terminal (items 405a or 405b) and a drain terminal (items 405a or 405b), each of the source and drain terminals (items 405a and 405b) extending through the dielectric material (item 415) and the second layer (items 402, 407 or 402 plus 407) and in contact with a top surface of the first layer (item 403).
In regards to claim 22, Yamazaki (Figs. 1B, 2B, 2C and associated text) discloses wherein the first metal includes tin, zinc, titanium, or copper (paragraph 106), and the second metal includes aluminum (aluminum, paragraphs 191, 184, 185, 195, 197).
In regards to claim 23, Yamazaki (Fig. 2C and associated text) discloses further comprising: a gate electrode (item 401) below the first layer (item 403); and a gate dielectric material (item 402) between the gate electrode (item 401) and the first layer (item 403).
Claim(s) 1-8, 11-17 and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sugawara (US 2017/0250289 A1).
In regards to claim 1, Sugawara (Fig. 4 and associated text) discloses an integrated circuit structure (Fig. 4), comprising: a first layer (item 140) comprising a semiconductor material (item 140, oxide semiconductor, paragraph 97); a second layer (items 151) above the first layer (item 140), the second layer (items 151) comprising a metal and one of oxygen or nitrogen (paragraph 104, aluminum oxide), wherein the second layer (items 151) has a thickness of at most 20 nanometers (nm) (paragraph 104, 5 nm to 40 nm); and a first source or drain terminal (items 160s or 160d) and a second source or drain terminal (items 160s or 160d), each of the first and second source or drain terminals (items 160s and 160d) extends through the second layer (item 151) and is landed on the first layer (item 140).
In regards to claim 2, Sugawara (Fig. 4 and associated text) discloses wherein the second layer (item 151) is an etch stop layer. Examiner notes that Sugawara (paragraph 104) discloses that the second layer (items 402, 407 or 402 plus 407) discloses a same material (aluminum oxide, an oxide or a nitride) as the Applicant [0045] “the etch stop layer 116 comprise an oxide or a nitride, such as aluminum oxide (Al.sub.2O.sub.3) in an example. For example, the etch stop layer 116 comprising aluminum oxide (or another appropriate oxide or a nitride)”. Therefore the second layer of Sugawara can share the same characteristics/functionality as an etch stop layer.
In regards to claim 3, Sugawara (Fig. 4 and associated text) discloses wherein the second layer (item 151) comprises aluminum and oxygen (paragraphs 104, aluminum oxide).
In regards to claim 4, Sugawara (Fig. 4 and associated text) discloses further comprising: a dielectric material (item 152) above the second layer (item 151), wherein the dielectric material (item 152) is elementally and/or compositionally different (silicon oxide) from the second layer (item 151, aluminum oxide).
In regards to claim 5, Sugawara (Fig. 4 and associated text) discloses wherein the dielectric material (item 152) is etch selective with respect to the second layer (item 151), such that an etch process to etch the dielectric material (item 152) doesn't substantially etch the second layer (items 151).
In regards to claim 6, Sugawara (Fig. 4 and associated text) discloses wherein the dielectric material (item 152) has a thickness of at least 25 nm (paragraph 104, 106, 495 nm or less), and wherein the thicknesses of the dielectric material (item 152) and the second layer (items 151) are measured in a direction perpendicular to a length of the first layer (item 140).
In regards to claim 7, Sugawara (Fig. 4 and associated text) discloses further comprising: a gate structure (items 120 plus 130) comprising (i) a gate electrode (item 130) and (ii) a gate dielectric material (item 130) that separates the first layer (item 140) from the gate electrode (item 120).
In regards to claim 8, Sugawara (Fig. 4 and associated text) discloses wherein the first layer (item 140) is above the gate structure (items 120 plus 130).
In regards to claim 11, Sugawara (Fig. 4 and associated text) discloses wherein the integrated circuit structure (Fig. 4) is a thin film transistor (TFT) structure (Fig. 4, paragraph 82, 83), with the first layer (item 140) being a thin film oxide semiconductor layer (item 140, paragraph 97) of the TFT (Fig. 4).
In regards to claim 12, Sugawara (Fig. 4 and associated text) discloses wherein the semiconductor material of the first layer (item 140) comprises an oxide semiconductor material (paragraph 97).
In regards to claim 13, Sugawara (Fig. 4 and associated text) discloses wherein the first source or drain terminal (items 160s or 160d) and the second source or drain terminal (items 160s or 160d) are each multilayer structures. Examiner takes official notice that it is well known in the art that conductive/metal structures/contacts/terminals can be single or multi-layered structures.
In regards to claim 14, Sugawara (Fig. 4 and associated text) discloses thin film transistor (TFT) structure (Fig. 4), comprising: a layer comprising a metal and oxygen (item 140 paragraphs 97); an etch stop layer on the layer comprising the metal and oxygen (items 151, aluminum oxide); a dielectric material (item 152) above the etch stop layer (item 151); and a source terminal and a drain terminal (items 160s and 160d), each of the source and drain terminals (items 160s and 160d) extending through the dielectric material (item 152) and the etch stop layer (item 151) and in contact with the layer comprising the metal and oxygen (item 140, paragraph 97).
In regards to claim 15, Sugawara (Fig. 4 and associated text) discloses further comprising: a gate electrode (item 120) below the layer comprising the metal and oxygen (item 140); and a gate dielectric material (item 130) between the gate electrode (item 120) and the layer comprising the metal and oxygen (item 140).
In regards to claim 16, Sugawara (Fig. 4 and associated text) discloses wherein the etch stop layer (item 151) is etch selective to the dielectric material (item 152), such that an etch process through the dielectric material (item 152) doesn't substantially etch the etch stop layer (item 152).
In regards to claim 17, Sugawara (Fig. 4 and associated text) discloses wherein the etch stop layer (item 151) comprises aluminum and oxygen (paragraph 104).
In regards to claim 21, Sugawara (Fig. 4 and associated text) discloses a thin film transistor (TFT) structure (Fig. 4), comprising: a first layer comprising a first metal and oxygen (item 140, paragraph 97); a second layer (item 151) directly on the first layer (item 140) and comprising a second metal (aluminum) and oxygen (paragraph 104), the second metal (aluminum) being different from the first metal (paragraph 106, zinc); a dielectric material (item 152) above the second layer (item 151); and a source terminal (item 160s) and a drain terminal (item 160d), each of the source and drain terminals (items 160s and 160d) extending through the dielectric material (item 152) and the second layer (item 151) and in contact with a top surface of the first layer (item 140).
In regards to claim 22, Sugawara (Fig. 4 and associated text) discloses wherein the first metal includes tin, zinc, titanium, or copper (paragraph 97), and the second metal includes aluminum (aluminum, paragraphs 104).
In regards to claim 23, Sugawara (Fig. 4 and associated text) discloses further comprising: a gate electrode (item 120) below the first layer (item 140); and a gate dielectric material (item 130) between the gate electrode (item 120) and the first layer (item 140).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See entire 892. Most references listed could have anticipated claim 1, 14 and 21 as currently written.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 April 12, 2026
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