DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 6, 7 and 10 are rejected under U.S.C. 103 as being unpatentable over Prakash et al.; US 2023/0307070 A1; 02/2022 in view of Kobayashi et al.; US 2021/0313334 A1; 02/2022 and Xie et al.; US 2023/0084615 A1; ( CON of PCT/CN2021/117882 filed 09/2021 )
Claim 1: Prakash discloses a semiconductor device, comprising: N number of decks ( Fig. 6B WLL0 – WLL10) that are stacked up in a Z direction ( Fig. 6B shows layers stacked in the Z direction ) and extend in parallel with an X-Y plane ( Fig. 6B is a cross section of one of the blocks in Fig. 6A) , N being an integer greater than 1 ( Fig. 6B N = 11), the X-Y plane being perpendicular to the Z direction ( Fig. 6B top right corner show perpendicular arrangement of X-Y plane, and Z ) and having an X direction and a Y direction perpendicular to the X direction ( Fig. 6B top right corner also shows X is perpendicular to Y ), each deck including alternating word line layers ( Fig. 6B WLL0 – WLL10 ) and insulating layers ( [0092] The block comprises a stack #610 of alternating conductive and dielectric layers ), wherein each deck includes two first gate line slit (GLS) structures ( Fig. 6B slits #617, #620 ) and a second GLS structure ( Fig. 6B memory hole #618, #619 ) positioned between the two first GLS structures ( Fig. 6B #617 and #620 ), the two first GLS structures ( Fig. 6B #617 and #620) and the second GLS structures ( Fig. 6B #618 and #619) each extending in an X-Z plane ( Fig. 6B shows the structures extend in the X-Z plane) and cutting through the word line layers and the insulating layers of the respective deck ( Fig. 6D is a zoomed in view of Fig 6B that shows the structures cut through the word line layers and the insulating layers).
Prakash does not appear to disclose at least one second GLS structure of at least one deck in the N number of decks including multiple sub-GLS structures, the multiple sub-GLS structures being separate from each other, and the second GLS structures of each deck forms a multi-deck GLS structure, the multi-deck GLS structure having a first sidewall in a first deck of the N number of decks, a second sidewall in a-second deck of the N number of decks, and a third sidewall at a border between the first deck and the second deck neighboring the first deck, an upper edge of the first sidewall and a lower edge of the second sidewall being staggered, the third sidewall connecting the first sidewall and the second sidewall, wherein the second GLS structures of at least two adjacent decks among the N number of decks have different numbers of distribution patterns along the X direction, each of the different distribution patterns being characterized by a respective distribution of respective separate sub-GLS structures included in the respective second GLS structure of the at least two adjacent decks.
However, Kobayashi teaches at least one second GLS structure ( Fig. 4: memory pillar MP ) of at least one deck ( Fig. 4: word lines WL0 to WL7) in the N number of decks ( Fig. 4: 16 decks ) including multiple sub-GLS structures ( Fig. 4: lower pillar LMP, and upper pillar UMP ), the multiple sub-GLS structures being separate from each other ( Fig. 4: illustrates LMP and UMP are separated from each other ) , and the second GLS structures of each deck forms a multi-deck GLS structure ( Fig. 4: LMP connects to WL0 to WL7 and UMP connects to WL8 to WL15 ), the multi-deck GLS structure having a first sidewall in a first deck of the N number of decks ( Fig. 4 : sidewall of LMP is in WL0 to WL7 ), a second sidewall in a-second deck of the N number of decks ( Fig 4 : sidewall of UMP is in WL 8 to 15 ), and a third sidewall at a border between the first deck and the second deck ( Fig. 4: JT ) neighboring the first deck ( Fig. 4 : LMP ), an upper edge of the first and a lower edge of the second sidewall being staggered sidewall ( Fig. 4: upper edge of LMP sidewall is wider than the lower edge of UMP ), the third sidewall connecting the first sidewall and the second sidewall ( Fig. 4 : JT connects the first sidewall and the second sidewall).
Kobayashi does not appear to disclose the second GLS structures of at least two adjacent decks among the N number of decks have different numbers of distribution patterns along the X direction, each of the different distribution patterns being characterized by a respective distribution of respective separate sub-GLS structures included in the respective second GLS structure of the at least two adjacent decks.
However, Xie teaches the second GLS structures ( Fig. 4B #438 ) of at least two adjacent decks among the N number of decks ( Fig. 4B: #433 ) have different numbers of distribution patterns along the X direction ( as shown in Fig. 4B ), each of the different distribution patterns being characterized by a respective distribution of respective separate sub-GLS structures included in the respective second GLS structure ( Fig. 4B : #438 has a different distribution pattern in region #423 than in regions #421-1 and #421-2 in the X direction ) of the at least two adjacent decks ( as shown in Fig. 4B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xie with Prakash and Kobayashi to implement the second GLS structures of at least two adjacent decks among the N number of decks have different numbers of distribution patterns along the X direction, each of the different distribution patterns being characterized by a respective distribution of respective separate sub-GLS structures included in the respective second GLS structure of the at least two adjacent decks because this optimized structural stability and improves etch uniformity.
Claim 2: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Prakash teaches the second GLS structure of each deck is located in a storage region ( [0092] Each NAND string encompasses a memory hole #618, #619 which is filled with materials which form memory cells adjacent to the word lines) of the semiconductor device ( [0090] Fig. 6A is a perspective view of a set of blocks #600 in an example three-dimensional configuration of the memory array #126 of Fig. 1 ) where memory cell strings ( Fig. 6B: NS1 and NS2 ) each along a channel structure are positioned ( Fig. 6D channel layer #665 ).
Claim 3: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Xie appear to disclose the second GLS structure of each deck has a same distribution pattern along the X direction, the distribution pattern being characterized by a distribution of separate sub-GLS structures included in the second GLS structure of each deck along the X direction.
However, Kobayashi teaches the second GLS structure of each deck has a same distribution pattern along the X direction ( Fig. 3: MP is distributed along the X direction ), the distribution pattern being characterized by a distribution of separate sub-GLS structures included in the second GLS structure of each deck along the X direction ( Fig. 3: MP is distributed along the X direction ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kobayashi with Prakash and Xie to implement the second GLS structure of each deck has a same distribution pattern along the X direction, the distribution pattern being characterized by a distribution of separate sub-GLS structures included in the second GLS structure of each deck along the X direction because uniformity allows for lithography and etching consistency in fabrication.
Claim 6: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Xie appear to disclose the second GLS structures of at least two nonadjacent decks among the N number of decks have a same distribution pattern along the X direction.
However, Kobayashi teaches the second GLS structures of at least two nonadjacent decks among the N number of decks have a same distribution pattern along the X direction ( Fig. 3: every other row has the same distribution in the X direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kobayashi with Prakash and Xie to implement the second GLS structures of at least two nonadjacent decks among the N number of decks have a same distribution pattern along the X direction because this approach balances manufacturing efficiency with the need for optimal device performance and reliability.
Claim 7: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Xie appear to disclose the second GLS structures of any two adjacent decks among the N number of decks have different distribution patterns along the X direction.
However, Kobayashi teaches the second GLS structures of any two adjacent decks ( Fig. 3: two adjacent rows) among the N number of decks ( Fig. 4: 16 decks ) have different distribution patterns along the X direction ( Fig. 3: shows two adjacent rows have different distribution patterns along the X direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kobayashi with Prakash and Xie to implement the second GLS structures of any two adjacent decks among the N number of decks have different distribution patterns along the X direction because this reduces interference between GLS structures.
Claim 10: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Xie appear to disclose a width at a top of a lower one of two neighboring second GLS structures of two neighboring decks is larger than a width at a bottom of an upper one of the two neighboring second GLS structures of the two neighboring decks in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure.
However, Kobayashi teaches a width at a top of a lower one of two neighboring second GLS structures of two neighboring decks ( Fig. 4: top of LMP) is larger than a width at a bottom of an upper one of the two neighboring second GLS structures ( Fig. 4: bottom of UMP) of the two neighboring decks in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure ( Fig. 4: illustrates the Y-Z plane ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kobayashi with Prakash and Xie to implement a width at a top of a lower one of two neighboring second GLS structures of two neighboring decks is larger than a width at a bottom of an upper one of the two neighboring second GLS structures of the two neighboring decks in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure because this can lead to improved electric field control.
Claim 5 is rejected under U.S.C. 103 as being unpatentable over Prakash et al.; US 2023/0307070 A1; 02/2022 in view of Kobayashi et al.; US 2021/0313334 A1; 02/2022 and Xie et al.; US 2023/0084615 A1; ( CON of PCT/CN2021/117882 filed 09/2021 ) as applied to claim 1 above and further in view of Russell et al.; US 2023/0307025 A1; 03/2022
Claim 5: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Kobayashi nor Xie appear to disclose the second GLS structures of at least two adjacent decks among the N number of decks have a same distribution pattern along the X direction.
However, Russell teaches the second GLS structures ( Fig. 2 conductive pillars #220-a-15 ) of at least two adjacent decks among the N number of decks have a same distribution pattern along the X direction ( Fig. 2 adjacent #220 pillars are distributed in a row ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Russell with Kobayashi, Prakash, and Xie to implement the second GLS structures of at least two adjacent decks among the N number of decks have a same distribution pattern along the X direction because the uniformity can lead to improved manufacturing and yield in the device.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Prakash et al.; US 2023/0307070 A1; 02/2022 in view of Kobayashi et al.; US 2021/0313334 A1; 02/2022 and Xie et al.; US 2023/0084615 A1; ( CON of PCT/CN2021/117882 filed 09/2021 ) as applied to claim 1 above and further in view of Iwai et al.; US 11114459 B2; 11/2019
Claim 8: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Kobayashi nor Xie appear to disclose the two first GLS structures of the N number of decks define a block structure between the two first GLS structures of the N number of decks, and the second GLS structures of the N number of decks define a border between two finger structures in the block structure.
However, Iwai teaches the two first GLS structures ( Fig. 1D #265 and #165 ) of the N number of decks ( Col. 9 lines 23 – 26 Each dielectric wall structure #76 can be located between a respective laterally neighboring set of alternating stacks of insulating layers (132, 232) ) define a block structure ( Fig. 1A memory array region #100 ) between the two first GLS structures ( Fig. 1D #265 and #165 ) of the N number of decks ( as discussed above ), and the second GLS structures of the N number of decks define a border between two finger structures ( Fig. 1C #76 ) in the block structure ( Fig. 1C is the array interconnect region #220) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Iwai with Kobayashi, Prakash, and Xie to implement the two first GLS structures of the N number of decks define a block structure between the two first GLS structures of the N number of decks, and the second GLS structures of the N number of decks define a border between two finger structures in the block structure because this approach can improve data management and access.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Prakash et al.; US 2023/0307070 A1; 02/2022 in view of Kobayashi et al.; US 2021/0313334 A1; 02/2022 and Xie et al.; US 2023/0084615 A1; ( CON of PCT/CN2021/117882 filed 09/2021 ) as applied to claim 1 above and further in view of Nagahata et al.; US 2022/0109003 A1; 10/2020
Claim 9: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Kobayashi nor Xie appear to disclose a width at a top of a lower one of two neighboring second GLS structures of two neighboring decks is smaller than a width at a bottom of an upper one of the two neighboring second GLS structures of the two neighboring decks in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure.
However, Nagahata teaches a width at a top of a lower one of two neighboring second GLS structures of two neighboring decks is smaller ( Fig. 5K bottom of slit) than a width at a bottom of an upper one of the two neighboring second GLS structures of the two neighboring decks ( Fig. 5K top of slit) in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure ( Fig. 5K is a cross-section view of a memory opening #49 of Figs. 4A and 4B)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nagahata with Kobayashi, Prakash, and Xie to implement a width at a top of a lower one of two neighboring second GLS structures of two neighboring decks is smaller than a width at a bottom of an upper one of the two neighboring second GLS structures of the two neighboring decks in a cross-section corresponding to a Y-Z plane passing the multi-deck GLS structure because varying the channel width potentially impacts the threshold voltage, trapped charge, and cell-to-cell interference.
Claim 11 is rejected under U.S.C. 103 as being unpatentable over Prakash et al.; US 2023/0307070 A1; 02/2022 in view of Kobayashi et al.; US 2021/0313334 A1; 02/2022 and Xie et al.; US 2023/0084615 A1; ( CON of PCT/CN2021/117882 filed 09/2021 ) as applied to claim 1 above and further in view of Kanakamedala et al.; US 9824966 B1; 08/2016
Claim 11: Prakash, Kobayashi, and Xie disclose the semiconductor device of claim 1 ( as discussed above).
Neither Prakash nor Kobayashi nor Xie appear to disclose two second GLS structures of two adjacent decks among the N number of decks have a first distribution pattern and a second distribution, respectively, along the X direction, the first distribution including sub-GLS structures separate at first positions, the second distribution including sub-GLS structures separate at second positions, the first positions and the second positions being staggered.
However, Kanakamedala teaches two second GLS structures of two adjacent decks among the N number of decks have a first distribution pattern ( Fig. 5B area #300) and a second distribution ( Fig. 5B areas #100 ), respectively, along the X direction, the first distribution including sub-GLS structures separate at first positions ( Fig. 5B support pillar structures #7P are in a row), the second distribution including sub-GLS structures separate at second positions ( Fig. 5B memory stack structure #55 are in staggered positions), the first positions and the second positions being staggered ( Fig. 5B the second positions of #55 are staggered ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kanakamedala with Kobayashi, Prakash, and Xie to implement two second GLS structures of two adjacent decks among the N number of decks have a first distribution pattern and a second distribution, respectively, along the X direction, the first distribution including sub-GLS structures separate at first positions, the second distribution including sub-GLS structures separate at second positions, the first positions and the second positions being staggered because this approach can be used to optimize the manufacturing process, improve electrical characteristics, and enhance the overall reliability and scalability of the device.
Response to Amendment/Argument
Applicant’s arguments, see page 5-6 of remarks, filed 11/28/2025, with respect to informalities in claim 1 have been fully considered and are persuasive. The objection of 08/28/2025 has been withdrawn.
Applicant’s arguments, see pages 6-7 of remarks, filed 11/28/2025, with respect to the rejection(s) of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Xie.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817 /MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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