DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 8 – 10, filed 09/10/2025, with respect to the rejections of claims 1-9 and 13-17 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 9, and 13 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kanemaru et al. (US 2009/0025961).
Regarding claim 1, Kanemaru teaches (FIG. 8, 9):
A component carrier (11), comprising:
a stack comprising a plurality of stacked layers, the stacked layers comprising at least one electrically conductive layer structure (12a, 12b) and at least one electrically insulating layer structure (13);
a plurality of equally designed electronic units (41) formed in the stack, each electronic unit comprising at least one semiconductor element embedded into the stack, wherein each semiconductor element is made of a semiconductor material ([0051]);
wherein at least a plurality of said electronic units are arranged to form at least one active area, which is surrounded by a frame area without functional components (FIG. 8);
a plurality of dummy components (51) embedded into the stack in the frame area;
wherein the at least a plurality of said electronic units is arranged in the at least one active area in a pattern (FIG. 8).
Kanemaru teaches various exemplary embodiments of uniform layouts of active and dummy structures for limiting warpage of a substrate, but fails to expressly disclose that active area components are arranged in a pattern comprising 5 rows or more and/or 5 columns or more.
However, it would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the active area devices in whatever arrangement of total devices was necessary or expedient for maximizing active area layout to minimize total device size while offsetting substrate stresses with dummy chip-like parts to achieve uniform stresses over the substrate, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 2, Kanemaru teaches:
The component carrier of claim 1, wherein each electronic unit comprises solely one semiconductor element ([0051]).
Regarding claim 3, Kanemaru teaches:
The component carrier of claim 1, wherein the at least one semiconductor element occupies at least more than at least 20% of a volume of the corresponding electronic unit ([0051] bare chip state).
Regarding claim 4, Kanemaru teaches (FIG. 8):
The component carrier of claim 1, wherein the at least a plurality of said electronic units in an active area are equally spaced and/or distributed in the rows and/or columns; and/or wherein a distance between two adjacent electronic units in the pattern is smaller than a width and/or thickness of the frame area.
Regarding claim 5, Kanemaru teaches (FIG. 8):
The component carrier of claim 1, wherein the dummy components are solely embedded into the frame area.
Regarding claim 6, Kanemaru teaches (FIG. 8):
The component carrier of claim 1, wherein at least some of the dummy components have an extension greater than an extension of the electronic units.
Regarding claim 7, Kanemaru teaches (FIG. 20):
The component carrier of claim 1, wherein an area of a dummy component is greater of at least 20 times the area of an electronic unit.
Regarding claim 8, Kanemaru teaches (FIG. 20):
The component carrier of claim 1, wherein at least some of the dummy components have an extension, which is greater than a distance between neighboring electronic units of the at least a plurality of said electronic units.
Regarding claim 9, Kanemaru teaches (FIG. 20):
The component carrier of claim 1, wherein the dummy components have different sizes.
Regarding claim 13, Kanemaru teaches (FIG. 20):
The component carrier of claim 1, wherein two dummy components have different shapes; and/or wherein at least one dummy component may be oriented in the component inclined with respect to a stack thickness direction and/or with respect to the electronic units of the active area.
Regarding claim 14, Kanemaru teaches ([0057]):
The component carrier of claim 1, wherein the dummy components are made of a homogenous material.
Regarding claim 15, Kanemaru teaches ([0057]):
The component carrier of claim 1, wherein the dummy components are made of a material comprising silicon.
Regarding claim 16, Kanemaru teaches ([0058]):
The component carrier of claim 1, wherein a coefficient of thermal expansion of the semiconductor elements differs at most by 10% from the coefficient of thermal expansion of at least some of the dummy components.
Regarding claim 17, Kanemaru teaches (FIG. 8):
The component carrier of claim 1, wherein the at least one active area is rectangular; and/or wherein the component carrier comprises a plurality of active areas, which are separated by strips composing the frame area; and/or wherein the active areas are arranged in rows and/or columns.
Claims 10 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kanemaru et al. (US 2009/0025961) as applied to claim 1 above, and further in view of Shih (US 9,607,967).
Regarding claim 10, Kanemaru fails to explicitly disclose:
The component carrier of claim 1, wherein a dummy component occupies at least two layers of the stack.
However, Shih (FIG. 15) teaches a multi-chip package having stiffening/warpage reducing components embedded with active components in multiple layers of the multi-chip stack (100a, 680).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply utilize the teachings of Kanemaru in multi-chip packages as taught by Shih for the predictable advantage of increasing device density while maintaining warpage control in a well-known manner.
Regarding claim 11, Kanemaru fails to explicitly disclose:
The component carrier of claim 1, wherein dummy components are arranged in at least two different layers of the stack.
However, Shih (FIG. 15) teaches a multi-chip package having stiffening/warpage reducing components embedded with active components in multiple layers of the multi-chip stack (100a, 680).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply utilize the teachings of Kanemaru in multi-chip packages as taught by Shih for the predictable advantage of increasing device density while maintaining warpage control in a well-known manner.
Regarding claim 12, Kanemaru fails to explicitly disclose:
The component carrier of claim 1, wherein dummy components are arranged in different layers as the semiconductor elements; and/or wherein two dummy components are stacked with respect to each other within the stack.
However, Shih (FIG. 15) teaches a multi-chip package having stiffening/warpage reducing components embedded with active components in multiple layers of the multi-chip stack (100a, 680).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply utilize the teachings of Kanemaru in multi-chip packages as taught by Shih for the predictable advantage of increasing device density while maintaining warpage control in a well-known manner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624