Prosecution Insights
Last updated: May 29, 2026
Application No. 18/090,199

METHOD AND DEVICE FOR OBTAINING COORDINATE OF CONTACT THROUGH-HOLE (CT) IN MEMORY DEVICE

Non-Final OA §103
Filed
Dec 28, 2022
Priority
Nov 29, 2022 — CN 202211511698.4
Examiner
CUTLER, ETHAN EDWARD
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
2 (Non-Final)
92%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
46 granted / 50 resolved
+24.0% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
10 currently pending
Career history
73
Total Applications
across all art units

Statute-Specific Performance

§103
93.8%
+53.8% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 50 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention has been amended in a curative manner; the objection is withdrawn. Response to Arguments Applicant's arguments filed 9/15/2025 have been fully considered but they are not persuasive. In particular, the Applicant argues that none of the cited references teach the limitations of the independent claims which have been added by amendment as of 9/15/2025. Because of the broadness of the claims, the concepts recited therein closely resemble data cleaning and quality improvement techniques (applicable to most types of data) widely known in the art. The claims apply these techniques in the field of BVC images and CT hole identification. For these reasons, the Rahm reference teaches the person of ordinary skill in the art all that they need to know in order to reach these limitations to improve data quality (as stated in the rejection of claims 1 and 11). It is suggested that the Applicant amend the claims to recite some technique, perhaps, as it pertains to the comparison of the CT coordinates in the BVC image, which would make the use of the Rahm reference untenable. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 2, 11, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20100320381 A1 to Zhao et al. (hereinafter “Zhao”) in view of Data Cleaning: Problems and Current Approaches to Rahm et al. (hereinafter “Rahm”). Regarding claim 1, Zhao teaches a method of locating contact through-hole (CT) (spots 421 which represent conductive plugs; fig. 4a) [0042] positions in a memory device (sample 40; fig. 4a) [0041], comprising: obtaining a bright voltage contrast (BVC) image (voltage contrast image 10 which is an image of sample 40; fig. 3) [0040] including a plurality of CTs (421) to be inspected (looked at) in the memory device (40); determining CT coordinates (defect distribution map produced through step 14; fig. 3) [0044] in the BVC image (10), the CT coordinates (14) in the BVC image including CT coordinates of the plurality of CTs to be inspected in the BVC image; validating (comparing the defect distribution map with a reference in step 18; fig. 3) [0048] the CT coordinates (14) in the BVC image (10) based on a golden CT layout (reference defect distribution map in step 18; fig. 3) [0048] to obtain validated CT coordinates (coordinates which are characterized) [0048] in the BVC image (10), wherein the golden CT layout (18) is arranged based on a design (reference image in step 18) of the memory device; and locating the CT positions (grey plugs 50 being less grey when compared to grey level 150) [0049] in the memory device based on the validated CT coordinates (characterized coordinates) in the BVC image (10). Zhao does not teach that the golden CT layout is for comparison with the CT coordinates (14) in the BVC image (10) and correcting the CT coordinates (14) in the BVC image (10) after the comparison is performed. Rahm, however, teaches data cleaning techniques (abstract) comparing the total data (verification step) (p. 7) with the design of the data (sample or copy of source data; verification step) (p. 7); and in response to the total data being different from the design of the data, prompt a person to manually correct data (multiple iterations through transformations; verification step) (p. 7). It would have been obvious to a person of ordinary skill in the art to clean the data (i.e., verify data against a reference and correct the data) used for the golden CT layout to improve data quality as taught by Rahm (p. 7). It is noted that the claims are directed to data manipulation and cleaning techniques in the context of CT layout verification and improvement. The cited references apply because there is no significant difference between the data handling techniques recited here (in the claims) and in theory (in the references). Regarding claim 2, Zhao in view of Rahm teaches the method according to claim 1, wherein validating the CT coordinates in the BVC image based on a golden CT layout to obtain the validated CT coordinates in the BVC image comprises: compare duplicated CT coordinates in the BVC image (10) [0050]; compare errored CT coordinates in the BVC image (10) [0050]; and compare missing CT coordinates in the BVC image (10) [0050]. To further clarify, Zhao teaches that the reference map is used and compared with the defect map and the result is then used to select spots for inspection [0050]. Zhao para. [0050] is interpreted as teaching the person of ordinary skill in the art to evaluate the data and thus “compare” which, in keeping with the broadest reasonable interpretation thereof, would suggest operations such as removing CT coordinates which are not fit and filling in gaps in the data to reconcile the two maps. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the process of Zhao to explicitly remove duplicated and errored CT coordinates while adding missing CT coordinates from the reference map to better select spots for inspection as taught by Zhao [0050]. Regarding claim 11, Zhao teaches a device of locating contact through-hole (CT) (spots 421 which represent conductive plugs; fig. 4a) [0042] positions in a memory device (sample 40; fig. 4a) [0041], comprising: a display screen (image forming module 718; fig. 7) [0061]; a memory storing program instructions (control module 731; fig. 7) [0060]; and a processor (image analysis module 732; fig. 7) [0059] configured to execute the program instructions stored in the memory (40) to: obtain a bright voltage contrast (BVC) image (voltage contrast image 10 which is an image of sample 40; fig. 3) [0040] including a plurality of CTs (421) to be inspected (looked at) in the memory device (40); determine CT coordinates (defect distribution map produced through step 14; fig. 3) [0044] in the BVC image (10), the CT coordinates (14) in the BVC image (10) including CT coordinates (14) of the plurality of CTs (421) to be inspected (looked at) in the BVC image (10); validate the CT coordinates (comparing the defect distribution map with a reference in step 18; fig. 3) [0048] in the BVC image (10) based on a golden CT layout (reference defect distribution map in step 18; fig. 3) [0048] to obtain validated CT coordinates (coordinates which are characterized) [0048] in the BVC image (10), wherein the golden CT layout (18) is arranged based on a design (reference image in step 18) of the memory device (40) and for comparison with the CT coordinates in the BVC image and correcting the CT coordinates in the BVC image after the comparison is performed; and locate the CT positions (grey plugs 50 being less grey when compared to grey level 150) [0049] in the memory device (40) based on the validated CT coordinates (characterized coordinates) in the BVC image (10). Zhao does not teach that the golden CT layout is for comparison with the CT coordinates (14) in the BVC image (10) and correcting the CT coordinates (14) in the BVC image (10) after the comparison is performed. Rahm, however, teaches data cleaning techniques (abstract) comparing the total data (verification step) (p. 7) with the design of the data (sample or copy of source data; verification step) (p. 7); and in response to the total data being different from the design of the data, prompt a person to manually correct data (multiple iterations through transformations; verification step) (p. 7). It would have been obvious to a person of ordinary skill in the art to clean the data (i.e., verify data against a reference and correct the data) used for the golden CT layout to improve data quality as taught by Rahm (p. 7). It is noted that the claims are directed to data manipulation and cleaning techniques in the context of CT layout verification and improvement. The cited references apply because there is no significant difference between the data handling techniques recited here (in the claims) and in theory (in the references). Regarding claim 12, Zhao in view of Rahm teaches the device according to claim 11, wherein when validating the CT coordinates in the BVC image based on a golden CT layout (18) to obtain validated CT coordinates (characterized coordinates) in the BVC image (10), the processor is further configured to execute the program instructions stored in the memory to: compare duplicated CT coordinates in the BVC image (10) [0050]; compare errored CT coordinates in the BVC image (10) [0050]; and compare missing CT coordinates in the BVC image (10) [0050]. To further clarify, Zhao teaches that the reference map is used and compared with the defect map and the result is then used to select spots for inspection [0050]. Zhao para. [0050] is interpreted as teaching the person of ordinary skill in the art to evaluate the data and thus “compare” which, in keeping with the broadest reasonable interpretation thereof, would suggest operations such as removing CT coordinates which are not fit and filling in gaps in the data to reconcile the two maps. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the process of Zhao to explicitly remove duplicated and errored CT coordinates while adding missing CT coordinates from the reference map to better select spots for inspection as taught by Zhao [0050]. Claims 3, 4, 9, 13, 14, & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Rahm as applied to claims 2 & 12 above, and further in view of U.S. Pat. Pub. No. US 20100314539 A1 to Xiao et al. (hereinafter “Xiao”). Regarding claim 3, Zhao in view of Rahm does not teach the method according to claim 2, wherein removing duplicated CT coordinates in the BVC image comprises: in response to a gap between two adjacent CT coordinates being smaller than or equal to 2 pixels, removing a smaller coordinate of the two adjacent CT coordinates. Xiao, however, teaches a method of identifying plug-to-plug electrical shorting (abstract) by comparing plug coordinates in a BVC image [0008], further comparing pixel by pixel [0032]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the removing step of Zhao to compare pixel by pixel to identify defects as taught by Xiao [0032]. Furthermore, the disclosure of Xiao [0032] establishes the prior art conditions necessary for the person or ordinary skill in the art to arrive at the numerical measure (smaller than or equal to 2 pixels) as a matter of routine optimization. M.P.E.P. 2144.05 II (A). Regarding claim 4, Zhao in view of Rahm does not teach the method according to claim 2, wherein removing errored CT coordinates in the BVC image comprises: calculating a gap between two adjacent CT coordinates in the BVC image; and in response to the gap between two adjacent CT coordinates being smaller than a minimum gap by design of the memory device, removing the two adjacent CT coordinates. Xiao, however, teaches a method of identifying plug-to-plug electrical shorting (abstract) by comparing plug coordinates in a BVC image [0008], further comparing pixel by pixel [0032]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the removing (errored) step of Zhao to compare the gaps (between pixels as taught by Xiao) between CT coordinates to identify defects as taught by Xiao [0032]. Furthermore, the disclosure of Xiao [0032] establishes the prior art conditions necessary for a person or ordinary skill in the art to arrive at the numerical measure (a gap falling below a pre-determined threshold) as a matter of routine optimization. M.P.E.P. 2144.05 II (A). Regarding claim 9, Zhao in view of Rahm does not teach the method according to claim 2, wherein: the CT coordinates in the BVC image include vertical CT coordinates and horizontal CT coordinates; and validation of the CT coordinates in the BVC image is performed separately for the vertical CT coordinates and the horizontal CT coordinates. Xiao, however, teaches CT coordinates including vertical CT coordinates (first image taken from one direction; fig. 3) [0028] and horizontal CT coordinates (second image from a second direction perpendicular to the first direction; fig. 3) [0028]; and validation of the CT coordinates in the BVC image is performed separately [0028] for the vertical CT coordinates and the horizontal CT coordinates. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify process of Zhao to validate the CT coordinates of vertical and horizontal coordinates separately to prepare both sets of CT coordinates for further processing as taught by Xiao [0028]. Regarding claim 13, Zhao in view of Rahm does not teach the device according to claim 12, wherein when removing duplicated CT coordinates (removing as modified) in the BVC image (10), the processor (732) is further configured to execute the program instructions stored in the memory to: calculate gaps between adjacent CT coordinates in the BVC image (10); and in response to a gap between two adjacent CT coordinates being smaller than or equal to 2 pixels, remove the smaller coordinate of the two adjacent CT coordinates (10). Xiao, however, teaches a method of identifying plug-to-plug electrical shorting (abstract) by comparing plug coordinates in a BVC image [0008], further comparing pixel by pixel [0032]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the removing step of Zhao to compare pixel by pixel to identify defects as taught by Xiao [0032]. Furthermore, the disclosure of Xiao [0032] establishes the prior art conditions and the person or ordinary skill in the art arriving at the numerical measure (smaller than or equal to 2 pixels) would have been a matter of routine optimization. M.P.E.P. 2144.05 II (A). Regarding claim 14, Zhao in view of Rahm does not teach the device according to claim 12, wherein when removing errored CT coordinates in the BVC image, the processor (732) is further configured to execute the program instructions stored in the memory to: calculate the gaps between adjacent CT coordinates in the BVC image; and in response to a gap between two adjacent CT coordinates being smaller than a minimum gap by design of the memory device, remove both of the two adjacent CT coordinates. Xiao, however, teaches a method of identifying plug-to-plug electrical shorting (abstract) by comparing plug coordinates in a BVC image [0008], further comparing pixel by pixel [0032]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the removing (errored) step of Zhao to compare the gaps between CT coordinates to identify defects as taught by Xiao [0032]. Furthermore, the disclosure of Xiao [0032] establishes the prior art conditions necessary for the person of ordinary skill in the art to arrive at the numerical measure (a gap falling below a pre-determined threshold) as a matter of routine optimization. M.P.E.P. 2144.05 II (A). Regarding claim 19, Zhao in view of Rahm does not teach the device according to claim 12, wherein: the CT coordinates in the BVC image include vertical CT coordinates and horizontal CT coordinates; and validation of the CT coordinates in the BVC image is performed separately for the vertical CT coordinates and the horizontal CT coordinates. Xiao, however, teaches CT coordinates including vertical CT coordinates (first image taken from one direction; fig. 3) [0028] and horizontal CT coordinates (second image from a second direction perpendicular to the first direction; fig. 3) [0028]; and validation of the CT coordinates in the BVC image is performed separately [0028] for the vertical CT coordinates and the horizontal CT coordinates. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify process of Zhao to validate the CT coordinates of vertical and horizontal coordinates separately to prepare both sets of CT coordinates for further processing as taught by Xiao [0028]. Claims 5 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Rahm as applied to claims 2 & 12 above, respectively, and further in view of Missing data imputation: focusing on single imputation to Zhang et al. (hereinafter “Zhang”). Regarding claim 5, Zhao in view of Rahm does not teach the method according to claim 2, wherein adding missing CT coordinates in the BVC image comprises: calculating a gap between two adjacent CT coordinates in the BVC image; comparing the gap in the BVC image with a corresponding gap in the golden CT layout; and in response to the gap in the BVC image being greater than the corresponding gap in the golden CT layout, adding a CT coordinate to reduce the gap in the BVC image. Zhang, however, teaches data imputation to fill in missing data (abstract) by comparing the relationship between the data i.e., regression imputation (abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the adding (missing) step of Zhao to compare the gaps between CT coordinates to fill in missing data while preserving correlation of surrounding data as taught by Zhang in the summary. Furthermore, the disclosure of Zhang (summary) establishes the prior art conditions necessary for the person or ordinary skill in the art to arrive at the CT gap filling limitations i.e., a gap being greater than a corresponding gap in the golden CT layout. Arriving at these limitations would have been a matter of routine optimization. M.P.E.P. 2144.05 II (A). Regarding claim 15, Zhao in view of Rahm does not teach the device according to claim 12, wherein when adding missing CT coordinates in the BVC image, the processor is further configured to execute the program instructions stored in the memory to: compare the gaps in the BVC image with corresponding gaps in the golden CT layout; and in response to a gap in the BVC image being greater than a corresponding gap in the golden CT layout, add a CT coordinates to reduce the gap in the BVC image. Zhang, however, teaches data imputation to fill in missing data (abstract) by comparing the relationship between data i.e., regression imputation (abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the adding (missing) step of Zhao to compare the gaps between CT coordinates to fill in missing data while preserving correlation of surrounding data as taught by Zhang in the summary. Furthermore, the disclosure of Zhang (summary) establishes the prior art conditions necessary for the person or ordinary skill in the art to arrive at the CT gap filling limitations (a gap being greater than a corresponding gap in the golden CT layout) as a matter of routine optimization. M.P.E.P. 2144.05 II (A). Claims 6, 7, 16, & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Zhang as applied to claims 5 & 15 above, and further in view of Xiao. Regarding claim 6, Zhao in view of Rahm and Zhang does not teach the method according to claim 5, further comprising: in response to a first gap in the BVC image being unequal to a corresponding first gap in the golden CT layout, marking the BVC image for manual inspection Xiao, however, teaches the identification (i.e., marking) [0032] of differing CT positions between patterns (images 510(a) and 511(a) for example). Xiao further teaches that these markings are made in response to gaps in the CT positions [0032]-[0035]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the mark unequal gaps in the CT positions to identify defects as taught by Xiao [0032]. Regarding claim 7, Zhao in view of Rahm, Zhang, and Xiao, as presently modified, does not teach the method according to claim 5, wherein: a deviation of less than or equal to two pixels between the gap in the BVC image and the corresponding gap in the golden CT layout verifies that the gap in the BVC image matches with the corresponding gap in the golden CT layout. Xiao, however, teaches a method of identifying plug-to-plug electrical shorting (abstract) by comparing plug coordinates in a BVC image [0008], further comparing pixel by pixel [0032]. Zhao in view of Zhang and Xiao establishes the prior art conditions (marking of positions based on pixels as taught by Xiao) necessary for a person of ordinary skill in the art to arrive at the gap validation limitations of claim 7 by routine experimentation. M.P.E.P. 2144.05 II (A). Regarding claim 16, Zhao in view of Rahm and Zhang does not teach the device according to claim 15, wherein the processor is further configured to execute the program instructions stored in the memory to: in response to the first gap in the BVC image being unequal to the corresponding first gap in the golden CT layout, mark the BVC image for manual inspection. Xiao, however, teaches the identification (i.e., marking) [0032] of differing CT positions between patterns (images 510(a) and 511(a) for example). Xiao further teaches that these markings are made in response to gaps in the CT positions [0032]-[0035]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the mark unequal gaps in the CT positions to identify defects as taught by Xiao [0032]. Regarding claim 17, Zhao in view of Rahm, Zhang, and Xiao, as presently modified, does not teach the device according to claim 16, wherein: a deviation of less than or equal to two pixels between the gap in the BVC image and the corresponding gap in the golden CT layout verifies that the gap in the BVC image matches with the corresponding gap in the golden CT layout. Zhao in view of Zhang and Xiao, however, establishes the prior art conditions (marking of position patterns as taught by Zhao in view of Zhang and Xiao) necessary for a person of ordinary skill in the art to arrive at the gap deviation limitations of claim 17 by routine experimentation. M.P.E.P. 2144.05 II (A). Claims 8 & 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Rahm, Zhang, and Xiao as applied to claims 7 & 17 above, as evidenced by Big Data Validation and Quality Assurance -- Issuses, Challenges, and Needs to Gao et al. (hereinafter “Gao”). Regarding claim 8, Zhao in view of Rahm, Zhang, and Xiao teaches the method according to claim 7, further comprising: compare (18) a total number of the CT coordinates (421) in the BVC image (10) with a total number of CT coordinates (421) by the design (reference image in step 18) of the memory device (40); and Zhao in view of Rahm, Zhang, and Xiao, as presently modified, does not teach in response to the total number of CT coordinates in the BVC image unequal to the total number of CT coordinates by the design of the memory device, marking the BVC image for inspection. Xiao, however, teaches the identification of abnormal plug patterns [0028] using numerous scans. Xiao further teaching comparing the scans with a database layout of the sample to find the abnormal plug patterns [0031]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify process of Zhao to further comprise an identification step to compare the identified plug patterns between the viewed and golden images to identify defects as taught by Xiao [0028] & [0043]. Zhao in view of Zhang and Xiao do not explicitly teach that the comparing a total number of CT coordinates with the design number occurs after the missing CT coordinates are added. This process, executed after the addition of missing data, is a validation process, and such is common as part of a data cleaning routine known to the person of ordinary skill in the art as evidenced by Gao fig. 2. Regarding claim 18, Zhao in view of Rahm, Zhang, and Xiao teaches the device according to claim 17, wherein the processor is further configured to execute the program instructions stored in the memory to: compare (18) a total number of CT coordinates (421) in the BVC image (10) with a total number of CT coordinates (421) by the design (reference image in step 18) of the memory device (40); and Zhao in view of Rahm, Zhang, and Xiao, as presently modified, does not teach in response to the total number of CT coordinates in the BVC image unequal to the total number of CT coordinates by the design of the memory device, mark the BVC image for inspection. Xiao, however, teaches the identification of abnormal plug patterns [0028] using numerous scans. Xiao further teaching comparing the scans with a database layout of the sample to find the abnormal plug patterns [0031]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify process of Zhao to further comprise an identification step to compare the identified plug patterns between the viewed and golden images to identify defects as taught by Xiao [0028] & [0043]. Zhao in view of Rahm, Zhang, and Xiao do not explicitly teach that the comparing a total number of CT coordinates with the design number occurs after the missing CT coordinates are added. This process, however, is a validation process, and such is common in the art as part of a data cleaning routine known to the person of ordinary skill in the art as evidenced by Gao fig. 2. Claims 10 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Rahm as applied to claim 1 & 11 above, and further in view of Gao and further in view of Rahm. Regarding claim 10, Zhao in view of Rahm does not teach the method according to claim 1, wherein the golden CT layout is obtained by: removing the duplicated CT coordinates in the BVC image; comparing the total number of CT coordinates in the BVC image with the total number CT coordinates by the design of the memory device wherein in response to the total number of CT coordinates in the BVC image being different from the total number CT coordinates by the design of the memory device, the CT coordinates in the BVC image are corrected based on the design of the memory device to obtain the golden CT layout. Gao, however, teaches: removing the duplicated data (data cleaning; fig. 2) (p. 436); removing the errored data (data cleaning; fig. 2) (p. 436); It would have been obvious to a person of ordinary skill in the art to clean the data (i.e., remove duplicate or errored data) used for the golden CT layout to improve data quality as taught by Gao (p. 436). Zhao in view of Rahm and Gao, as presently modified, does not teach comparing the total number of CT coordinates in the BVC image with the total number CT coordinates by the design of the memory device; and in response to the total number of CT coordinates in the BVC image being different from the total number CT coordinates by the design of the memory device, the Ct coordinates in the BVC image are corrected based on the design of the memory device to obtain the golden CT layout. Rahm, however, teaches data cleaning techniques (abstract) comparing the total data (verification step) (p. 7) with the design of the data (sample or copy of source data; verification step) (p. 7); and in response to the total data being different from the design of the data, prompt a person to correct data (multiple iterations through transformations; verification step) (p. 7). It would have been obvious to a person of ordinary skill in the art to clean the data (i.e., verify data against a reference) used for the golden CT layout to improve data quality as taught by Rahm (p. 7). It is noted that the above claim is directed to data manipulation and cleaning techniques in the context of CT layout verification and improvement. The cited references apply because there is no significant difference between the data handling techniques recited here (in claim 20) and in theory (in the references). The techniques seem to be simple data handling techniques which are applied to BVC images of CT coordinates. Regarding claim 20, Zhao in view of Rahm does not teach the device according to claim 11, wherein in a step of obtaining the golden CT layout, the processor is further configured to execute the program instructions stored in the memory to: remove the duplicated CT coordinates in the BVC image; remove the errored CT coordinates in the BVC image; compare the total number of CT coordinates in the BVC image with the total number CT coordinates by the design of the memory device; and in response to the total number of CT coordinates in the BVC image being different from the total number CT coordinates by the design of the memory device, prompt an instruction for correcting the CT coordinates in the BVC image. Gao, however, teaches: removing the duplicated data (data cleaning; fig. 2) (p. 436); removing the errored data (data cleaning; fig. 2) (p. 436); It would have been obvious to a person of ordinary skill in the art to clean the data (i.e., remove duplicate or errored data) used for the golden CT layout to improve data quality as taught by Gao (p. 436). Zhao in view of Rahm and Gao, as presently modified, does not teach comparing the total number of CT coordinates in the BVC image with the total number CT coordinates by the design of the memory device; and in response to the total number of CT coordinates in the BVC image being different from the total number CT coordinates by the design of the memory device, prompt a person to manually correct the CT coordinates in the BVC image. Rahm, however, teaches data cleaning techniques (abstract) comparing the total data (verification step) (p. 7) with the design of the data (sample or copy of source data; verification step) (p. 7); and in response to the total data being different from the design of the data, prompt a person to manually correct data (multiple iterations through transformations; verification step) (p. 7). It would have been obvious to a person of ordinary skill in the art to clean the data (i.e., verify data against a reference) used for the golden CT layout to improve data quality as taught by Rahm (p. 7). It is noted that the claims are directed to data manipulation and cleaning techniques in the context of CT layout verification and improvement. The cited references apply because there is no significant difference between the data handling techniques recited here (in claim 20) and in theory (in the references). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ETHAN EDWARD CUTLER/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Dec 28, 2022
Application Filed
Jun 17, 2025
Non-Final Rejection mailed — §103
Sep 15, 2025
Response Filed
Dec 17, 2025
Final Rejection mailed — §103
Feb 11, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641828
STACKED FET STRUCTURES WITH DIFFERENT GATE DIELECTRIC COMPOSITIONS OR THICKNESSES
3y 5m to grant Granted May 26, 2026
Patent 12635169
SEMICONDUCTOR DEVICE
3y 5m to grant Granted May 19, 2026
Patent 12628383
TRANSISTORS HAVING STACKED 2D MATERIAL CHANNEL LAYERS AND HETEROGENEOUS 2D MATERIAL CONTACTS LAYERS EPITAXIAL TO THE 2D MATERIAL CHANNEL LAYERS
4y 7m to grant Granted May 12, 2026
Patent 12628700
LED DISPLAY APPARATUS
2y 10m to grant Granted May 12, 2026
Patent 12622185
METHOD FOR MANUFACTURING SEMICONDUCTOR SILICON WAFER COMPOSED OF SILICON WAFER SUBSTRATE AND SILICON MONOCRYSTALLINE EPITAXIAL LAYER
3y 9m to grant Granted May 05, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

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Prosecution Projections

2-3
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+12.1%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 50 resolved cases by this examiner. Grant probability derived from career allowance rate.

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