Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
This is a response to the election filed on 1/26/2026.
Claims 1-14 = elected without traverse.
Claims 15-25 = canceled
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 8-11 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Oriordan (US 2023/0351088)
Regarding claim 1, the prior art discloses:
An apparatus to adjust at least one via in an IC based on machine learning (title), the apparatus comprising:
at least one memory; machine readable instructions; and processor circuitry (tools/ EDA/computer in par 2, fig 40) to at least one of instantiate or execute the machine readable instructions to:
compute a dimension by which to extend a first via based on at least one of a first metal wire in a first layer of the IC above the first via, a via-to-via patterning constraint, or a via-to-metal shorting constraint for a second layer of the IC below the first via (see one or more of:
via-to-via extension rules/ constraints in par 98, dimension is one or more of wire width, spacing, extend amount;
layer misalignment problem to result in poor via/contact overlaps, short (par 6, 63);
modifying routes to perform any of these via modification operations (par 186);
movement of the via along a route can include modification of the route to extend to a new location of the via on one or more interconnect layers (par 172);
par 196:( via-modification operation) modifies any route for which the operation added redundant vias or moved vias…new constraints (e.g., location constraints, via location constraints);
compute a shifted position of the first via based on at least one of (a) the dimension or (b) a width and a position of a second metal wire below the first via, the width and the position predicted by an ML model (see one or more of:
par 39-41: moving/modifying vias involving neural network/ machine train network (MTN) for prediction/ identification/ approximation of via shape;
par 165, 168, 172-175 : MTM identify candidate via location… move via…movement of the via along a route can include modification of the route to extend to a new location of the via on one or more interconnect layers;
par 183: compute the predicted via overlap shape…predicted overlap shape for the particular via accounts for structures that neighbor this via on different layers
par 186-188: via location modification/move MTN,
par 189: MTN to generate the predicted manufactured shapes of vias, and then analyzes these shapes to determine whether it needs to insert additional redundant vias and/or to move any vias); and
adjust a configuration file (one or more of:
adjusting parameter values/contours of parameterized mask process, factoring OPC, manufacturing parameters (par 77-79, 131),
adjust a set of trainable parameters of the MTN (par 173);
configurable parameters/values to be configured/adjusted (par 185, 220);
adjustable set of trainable parameters (par 188) ) corresponding to the IC based on at least one of the dimension or the shifted position of the first via.
(Claim 2) wherein the width and the position of the second metal wire predicted by the ML model is to identify the width and the position of the second metal wire after application of a process window optimization technique (fig 20-25, 33-36).
(Claim 3) wherein the second metal wire is in the second layer of the IC, and the processor circuitry is to: compute the dimension by which to extend the first via based on the configuration file indicating that the first layer of the IC was designed with flexible pitch design rules (par 20, 81, 94, 98-9981); and predict, with the ML model, the width and the position of the second metal wire based on the configuration file indicating that the second layer of the IC was designed with flexible pitch design rules (par 131, 158, 178, 191, 195).
(Claim 4) wherein the via-to-metal shorting constraint for the second layer is a first via-to-metal shorting constraint (par 63-65, 82, 98, 126, 169, 183, 193, 246), and the processor circuitry is to adjust the shifted position of the first via based on the shifted position violating at least one of the via-to-via patterning constraint, a second via-to-metal shorting constraint for the first layer, or the first via-to- metal shorting constraint for the second layer constraint (par 63-65, 82, 98, 126, 169, 183, 193, 246),
Claims 8-11 recite similar subject matter and are rejected for the same reason.
Allowable Subject Matter
Claims 5-7 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5-7 and 12-14 would be allowable because the prior art does not teach or suggest:
The limitation in claim 5 and similarly recited claim 12;
The limitation in claim 6 and similarly recited claim 13;
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851