DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-9 and 14 are objected to because of the following informalities:
In claim 1, line 6, substitute “the least[DM1]” with –the at least-- before “two capacitor dielectric layers.”
In claim 8, line 1, add --at least two-- before “capacitor dielectric layers.”
In claim 14, line 2, add --at least two-- before “capacitor dielectric layers.”
Claims 2-7 and 9 depend from claim 1, so they are objected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inoue et al. (US Pub. 2009/0309186; hereinafter “Inoue”).
Regarding Claim 1, Inoue discloses an apparatus, comprising: an insulative material layer 20 (page 4, paragraph 36), the insulative material layer 20 comprising at least a portion of a package substrate or a build-up layer on the package substrate (a substrate 1, an inter-layer insulating film 10, and an inter-passive element layer insulating film 20 collectively form a package substrate, and the inter-passive element layer insulating film 20 forms part of the package substrate; see fig. 1); a multi-layer capacitor structure 55 (page 4, paragraph 37) at least partially within an opening 32 (page 5, paragraph 43) extending through the insulative material layer 20 (see figs. 1 and 2C), the multi-layer capacitor structure 55 comprising at least two capacitor dielectric layers (52, 44) (page 4, paragraph 37) interleaved with a plurality of conductive layers (51, 53) (page 4, paragraph 37; see fig. 1), the at least two capacitor dielectric layers (52, 44) at least partially within the opening 32 and a first of the conductive layers 51 on a sidewall of the opening 32 (see figs. 1 and 2E); and first and second terminals (11, 63) (page 4, paragraph 38) coupled to the multi-layer capacitor structure 55 (page 4, paragraph 38; see fig. 1).
Regarding Claim 4, Inoue discloses wherein each of the least two capacitor dielectric layers (52, 44) and the plurality of conductive layers (51, 53) extend over a top surface of the insulative material layer 20 (see figs. 1 and 2E).
Regarding Claim 5, Inoue discloses wherein the first terminal 11 comprises a metallization layer (Cu wiring layer; page 4, paragraph 38) in contact with the first conductive layer 51 under the opening 32 (page 4, paragraph 38; see figs. 1 and 2E), wherein the sidewall extends from the metallization layer (Cu wiring layer) to a top surface of the insulative material layer 20 (see figs. 1 and 2C).
Regarding claim 7, Inoue discloses wherein the conductive layers (51, 53) comprise a metal (page 5, paragraphs 44 and 45).
Regarding Claim 8, Inoue discloses wherein the at least two capacitor dielectric layers (52, 44) comprise one of silicon and oxygen or silicon and nitrogen (silicon nitride; page 5, paragraphs 44 and 45).
Regarding Claim 9, Inoue discloses wherein the insulative material layer 20 comprises the portion of the package substrate (the substrate 1, the inter-layer insulating film 10, and the inter-passive element layer insulating film 20 collectively form the package substrate, and the inter-passive element layer insulating film 20 forms part of the package substrate; see fig. 1), the package substrate comprising an inorganic package substrate 1 (a semiconductor substrate; page 4, paragraph 36; see fig. 1).
Claims 16, 17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsui et al. (US Pat. 10,269,894; hereinafter “Tsui”).
Regarding Claim 16, Tsui discloses a system, comprising: a package substrate 202 (col. 3, lines 3-23) and a multi-layer capacitor 205 (col. 3, lines 40-50) at least partially embedded therein (see fig. 1A), the multi-layer capacitor 205 comprising: a multi-layer capacitor structure 205 at least partially within an opening 206 (col. 7, lines 51-67) extending through at least a portion of the package substrate 202 or a build-up layer thereon (see figs. 1A and 2C), the multi-layer capacitor structure 205 comprising at least two capacitor dielectric layers (210, 213, 216) (col. 4, lines 7-13) interleaved with a plurality of conductive layers (212, 214, 218) (col. 4, lines 3-6; see fig. 1A), the least two capacitor dielectric layers (210, 213, 216) at least partially within the opening 206 (see fig. 1A); and first and second terminals (244, 246) (col. 4, lines 40-43) coupled to the multi-layer capacitor structure 205 (see fig. 1A); and an integrated circuit device over and electrically coupled to the package substrate 202 (a metal layer 250 is configured to electrically connect the device or components with other devices on the semiconductor substrate 202; col. 4, lines 48-51; so, an integrated circuit device can be disposed above and electrically connected to the multi-layer capacitor 205 embedded in the substrate 202).
Regarding Claim 17, Tsui discloses wherein a package level interconnect 254 of the integrated circuit device is in contact with the first terminal 244 (see fig. 1A).
Regarding Claim 19, Tsui discloses wherein the first terminal 244 comprises a first conductive via 244 (col. 4, lines 40-43) in contact with a first conductive layer 212 of the conductive layers (212, 214, 218) at a first distance from the opening 206 (see fig. 1A). and the second terminal 246 comprises a second conductive via 246 (col. 4, lines 40-43) in contact with a second conductive layer 214 of the conductive layers (212, 214, 218) at a second distance, less than the first distance, from the opening 206 (see fig. 1A).
Regarding Claim 20, Tsui discloses wherein the multi-layer capacitor 205 further comprises a third conductive via 248 (col. 4, lines 40-43) in contact with a third conductive layer 218 of the conductive layers (212, 214, 218) at a position above the opening 206 (see fig. 1A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of Lee et al. (US Pub. 2009/0161298; hereinafter “Lee”).
Regarding Claim 2, Inoue fails to disclose explicitly wherein the opening comprises a via opening having a substantially circular cross section.
However, Lee discloses a circular through hole is provided where a circular through hole capacitor 900a is formed (page 3, paragraph 36; see fig. 9A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an opening comprising a circular via opening, as taught by Lee, thereby achieving electrical, mechanical, and fabrication uniformity resulting from the circular symmetry of the capacitor structure.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue.
Regarding Claim 3, Inoue discloses wherein the opening 32 comprises a trench opening 32 (see fig. 2C) having a length and a substantially orthogonal width (a length and a width in the XY plane in a top view).
Inoue fails to disclose explicitly wherein the length not less than three times the width.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because determining optimum process conditions would have involved no more than routine experimentation using a limited number of result-effective variables. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Furthermore, providing a specific dimension of an opening of the capacitor structure enables control of the capacitance and ensures stable electrical performance.
Claims 6 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of Tsui.
Regarding Claim 6, Inoue fails to disclose explicitly wherein the second terminal comprises a second conductive layer of the plurality of conductive layers.
However, Tsui discloses a plug 224 (a terminal) which is configured as an extension of a top electrode 218, and thus regarded as a portion of the capacitor 205 (col. 5, lines 7-11). Also, the plug 224 is made of a same material as a top electrode 218 of the capacitor 205 (col. 5, lines 7-11). Therefore, the plug 224 comprises the top electrode 218.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a terminal comprising a conductive layer of a capacitor structure, as taught by Tsui, in order to reduce interconnection resistance and improve electrical performance and reliability.
Regarding Claim 10, Inoue discloses an apparatus, comprising: an insulative material layer 20 (page 4, paragraph 36), the insulative material layer 20 comprising at least a portion of a package substrate or a build-up layer on the package substrate (a substrate 1, an inter-layer insulating film 10, and an inter-passive element layer insulating film 20 collectively form a package substrate, and the inter-passive element layer insulating film 20 forms part of the package substrate; see fig. 1); a multi-layer capacitor structure 55 (page 4, paragraph 37) at least partially within an opening 32 (page 5, paragraph 43) extending through the insulative material layer 20 (see figs. 1 and 2C), the multi-layer capacitor structure 55 comprising at least two capacitor dielectric layers (52, 44) (page 4, paragraph 37) interleaved with conductive layers (51, 53) (page 4, paragraph 37; see fig. 1), the at least two capacitor dielectric layers (52, 44) at least partially within the opening 32.
Inoue fails to disclose explicitly wherein a first conductive via in contact with a first conductive layer of the conductive layers at a first distance from the opening along a top surface of the insulative material layer; and a second conductive via in contact with a second conductive layer of the conductive layers at a second distance, less than the first distance, from the opening along the top surface of the insulative material layer.
However, Tsui discloses wherein a first conductive via 244 (col. 4, lines 40-43) in contact with a first electrode 212 at a first distance from an opening 206 (see fig. 1A), and a second conductive via 246 (col. 4, lines 40-43) in contact with a second electrode 214 at a second distance, less than the first distance from the opening 206 (see fig. 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first conductive via and a second conductive via positioned at different distances from an opening of the capacitor and connected to different electrodes of the capacitor, as taught by Tsui, in order to facilitate controlled routing and stable electrical connection, and to enable independent electrical connection to the respective electrodes.
Regarding Claim 11, Inoue discloses wherein the second conductive layer 53 is over the first conductive layer 51 and separated by a first capacitor dielectric layer 52 of the at least two capacitor dielectric layers (52, 44) therebetween (see fig. 1).
Regarding Claim 12, Inoue fails to disclose explicitly wherein further comprising: a third conductive via in contact with a third conductive layer of the conductive layers at a position above the opening.
However, Tsui discloses wherein a third conductive via 248 (col. 4, lines 40-43) in contact with a third electrode 218 at a position above the opening 206 (see fig. 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a third conductive via in contact with a third electrode of the capacitor at a position above the opening, as taught by Tsui, in order to facilitate interlayer electrical connection within a multilayer structure.
Regarding Claim 13, Inoue discloses wherein further comprising a metallization layer 11 (Cu wiring layer; page 4, paragraph 38) in contact with the first conductive layer 51 at a position below the opening 32 (page 4, paragraph 38; see figs. 1 and 2E), wherein a sidewall at least partially defining the opening 32 extends from the first conductive layer 51 to the top surface of the insulative material layer 20 (see fig. 1).
Regarding claim 14, Inoue discloses wherein the conductive layers (51, 53) comprise a metal (page 5, paragraphs 44 and 45) and the at least two capacitor dielectric layers (52, 44) comprise one of silicon and oxygen or silicon and nitrogen (silicon nitride; page 5, paragraphs 44 and 45).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of Tsui, and further in view of Lee.
Regarding Claim 15, Inoue in view of Tsui fails to disclose explicitly wherein the opening comprises a via opening having a substantially circular cross section.
However, Lee discloses a circular through hole is provided where a circular through hole capacitor 900a is formed (page 3, paragraph 36; see fig. 9A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an opening comprising a circular via opening, as taught by Lee, thereby achieving electrical, mechanical, and fabrication uniformity resulting from the circular symmetry of the capacitor structure.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tsui in view of Lee.
Regarding Claim 18, Tsui fails to disclose explicitly wherein the opening comprises a via opening having a substantially circular cross section.
However, Lee discloses a circular through hole is provided where a circular through hole capacitor 900a is formed (page 3, paragraph 36; see fig. 9A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an opening comprising a circular via opening, as taught by Lee, thereby achieving electrical, mechanical, and fabrication uniformity resulting from the circular symmetry of the capacitor structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 February 19, 2026