DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29 and 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 29 recites the limitation "the bottom cover portion" in the last two lines of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 30 recites the limitation "the bottom cover portion" in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-8, 21, and 23-31 are rejected under 35 U.S.C. 102 as being anticipated by Jung et al. ( US 2023/0014037 A1; hereinafter Jung )
Regarding claim 1, Jung teaches a three-dimensional memory device ( [0034] The semiconductor device 1100 may be a nonvolatile memory device (e.g., a NAND FLASH memory device)), comprising: a plurality of stacked layers ( Fig. 7 EL and ILD; [0067] The electrode structure ST may include electrodes EL and insulating patterns ILD, which are alternately stacked in a direction perpendicular to the top surface of the lower semiconductor layer #100 ); a storage channel structure ( Fig. 7: VS ; [0151] The vertical structure VS may include a data storage layer, a channel layer, a gapfill insulating layer, a pad, and so forth ) vertically penetrating the stacked layers ( as shown in Fig. 7 ) and comprising a first channel layer ( Fig. 7: channel hole CH; [0070] Each of the vertical structures VS may be provided in channel holes CH; which are formed to penetrate the electrode structure ST ); a select gate structure ( Fig. 7: bit line BL) on the plurality of stacked layers ( Fig. 8 is a zoomed in section of Fig. 7 with the stacked layers ); and a select channel structure ( Fig. 7: bit line BL ) vertically penetrating the select gate structure ( Fig. 7: contact plugs BPLG; [0106] The bit lines BL may be electrically connected to the upper channel structures UCS, respectively through the contact plugs BPLG ) and comprising a second channel layer ( Fig. 7: UCS ); wherein an outer sidewall ( Fig. 8: outer sidewall of CPB ) of the second channel layer ( Fig. 8: UCS; [0092] In an embodiment, the upper semiconductor pattern USP and the conductive pattern CP may be connected to form a single object or unitary structure) is in contact with an inner sidewall ( Fig. 8: portion where CPb contacts the sidewall of VS; [0086] A lower portion of the conductive pattern CP may be provided to penetrate the capping pattern IP and may be connected to the conductive pad PD of the vertical structure VS ) of the first channel layer ( Fig. 8: VS ) and an overlap length of a contact interface ( Fig. 8: t1 – t2 ) between the second channel layer ( Fig. 8: UCS ) and the first channel layer ( Fig. 8: VS ) in a vertical direction ( as shown in Fig. 8 ) is greater than a thickness of the first channel layer ( as shown in Fig. 8 the overlap of t1-t2 is thicker than the layers of VS: SP, and individual layers of VP; [0105] A portion of the conductive pattern CP having the protruding portion PP may have the largest thickness t1, and another portion of the conductive pattern CP overlapped with the insulating pattern ILD may have the smallest thickness t2, with a step difference therebetween ).
Regarding claim 4, Jung teaches the memory device of claim 1 (as discussed above), wherein the plurality of stacked layers ( Fig. 7: electrode structure ST ) comprise a plurality of alternatively stacked first conductive layers ( Fig. 7: electrodes EL ) and first dielectric layers ( Fig. 7 insulating patterns ILD ) ; and the select gate structure ( Fig. 7: bit line BL) comprises a second conductive layer ( Fig. 7: UHL ) and two second dielectric layers ( Fig. 7 #131 and #122 ; [0085] For example, the second insulating layer 122 may be formed of or include silicon oxide ; [0089] The first and second interlayer insulating layers 131 and 141 may be formed of or include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride ) on a top surface ( Fig. 7 #131 ) and a bottom surface ( Fig. 7 #122 ) of the second conductive layer ( Fig. 7: UHL ).
Regarding claim 5, Jung teaches the memory device of claim 4 ( as discussed above), wherein the first conductive layers ( Fig. 7: EL; [0067] Each of the electrodes EL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum )) and the second conductive layer ( Fig. 7: UHL; [0088] The upper horizontal electrode UHL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum)) have different materials ( Rhe EL and UHL can elect different materials from the lists above).
Regarding claim 6, Jung discloses the memory device of claim 5 (as discussed above), wherein: the first conductive layer ( Fig. 7: EL) comprises a metal ( [0067] Each of the electrodes EL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum ); metallic materials in the list ); and the second conductive layer ( Fig. 7: UHL ) comprises one of polysilicon, doped polysilicon, and metal silicide ( [0088] The upper horizontal electrode UHL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum); doped semiconductor materials in the list ).
Regarding claim 7, Jung teaches the memory device of claim 1 (as discussed above), wherein the select channel structure ( Fig. 7: BL ) further comprises: a second dielectric core ( Fig. 8: upper gapfill insulating pattern UVI) horizontally surrounded by the second channel layer ( Fig. 8: UCS ); and an insulating layer ( Fig. 8: second interlayer insulating layer #141 ) between the second channel layer ( Fig. 8: UCS ) and the select gate structure ( Fig. 7: BL ).
Regarding claim 8, Jung teaches the memory device of claim 7, wherein: the insulating layer ( Fig. 8 #141 ) covers a top surface of the first channel layer ( Fig. 8: UCS ).
Regarding claim 21, Jung teaches a three-dimensional memory device ( [0034] The semiconductor device 1100 may be a nonvolatile memory device (e.g., a NAND FLASH memory device)), comprising: a plurality of stacked layers ( Fig. 7 EL and ILD; [0067] The electrode structure ST may include electrodes EL and insulating patterns ILD, which are alternately stacked in a direction perpendicular to the top surface of the lower semiconductor layer #100 ); a storage channel structure ( Fig. 7: VS ; [0151] The vertical structure VS may include a data storage layer, a channel layer, a gapfill insulating layer, a pad, and so forth ) vertically penetrating the stacked layers ( as shown in Fig. 7 ) and comprising a first channel layer ( Fig. 7: channel hole CH; [0070] Each of the vertical structures VS may be provided in channel holes CH; which are formed to penetrate the electrode structure ST ); a select gate structure ( Fig. 8: CL2; [0076] The charge storing layer CL2 may be a trap insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots ) on the plurality of stacked layers ( Fig. 8 is a zoomed in section of Fig. 7 with the stacked layers ); and a select channel structure ( Fig. 7: bit line BL ) vertically penetrating the select gate structure ( Fig. 7: contact plugs BPLG; [0106] The bit lines BL may be electrically connected to the upper channel structures UCS, respectively through the contact plugs BPLG ) and comprising a second channel layer ( Fig. 7: UCS ); wherein the second channel layer comprises a vertical portion ( Fig. 8: upper insulating pattern UVP ) and a bottom portion ( Fig. 8: CP ) , and the bottom portion encloses a lower end of the vertical portion ( as shown in Fig. 8 ) and is in contact with the first channel layer ( Fig. 8: VS).
Regarding claim 23, Jung teaches the memory device of claim 21 (as discussed above), wherein the second channel layer ( Fig. 8: UCS) extends into the storage channel structure ( Fig. 8: CP extends into VS ), and further in contact with a top surface of a first dielectric core ( Fig. 8: VI) of the storage channel structure ( Fig. 8: VS ).
Regarding claim 24, Jung teaches the memory device of claim 21 (as discussed above), wherein: the plurality of stacked layers ( Fig. 7: ST ) comprise a plurality of alternatively stacked first conductive layers ( Fig. 7: EL ) and first dielectric layers ( Fig. 7: ILD ) ; and the select gate structure ( Fig. 7: BL ) comprises a second conductive layer ( Fig. 7: upper horizontal electrode UHL ) and two second dielectric layers ( Fig. 7 first interlayer insulating layer #131 and second insulating layer #122 ) on a top surface ( Fig. 7: #131 ) and a bottom surface ( Fig. 7 #122 ) of the second conductive layer ( Fig. 7: UHL ).
Regarding claim 25, Jung teaches the memory device of claim 24 ( as discussed above), wherein the first conductive layers ( [0067] Each of the electrodes EL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum). Each of the insulating patterns ILD may be formed of or include silicon oxide) and the second conductive layer ( [0088] The upper horizontal electrode UHL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum)) have different materials ( as shown above the EL and UHL may be different materials from each other )
Regarding claim 26, Jung teaches the memory device of claim 25 (as discussed above), wherein: the first conductive layer comprises a metal ( [0067] Each of the electrodes EL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum). Each of the insulating patterns ILD may be formed of or include silicon oxide; a metal material is in the list ); and the second conductive layer comprises one of polysilicon, doped polysilicon, and metal silicide ( [0088] The upper horizontal electrode UHL may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, copper or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum); doped polysilicon is a doped semiconductor material ).
Regarding claim 27, Jung teaches the memory device of claim 21 (as discussed above), wherein the select channel structure further comprises: a second dielectric core ( Fig. 8: UVI ) horizontally surrounded by the second channel layer ( Fig. 8: UCS ) ; and an insulating layer ( Fig. 7: #141 ) between the second channel layer ( Fig. 7: UCS ) and the select gate structure ( Fig. 7: BL ).
Regarding claim 28, Jung teaches the memory device of claim 27 ( as discussed above), wherein: the insulating layer ( Fig. 8 #122 ) covers a top surface of the first channel layer ( Fig. 8: VS ).
Regarding claim 29, Jung teaches the memory device of claim 27 ( as discussed above), wherein the storage channel structure ( Fig. 8: VS ) further comprises: a first dielectric core ( Fig. 8: VI ) horizontally surrounded by the first channel layer ( Fig. 8: VS ), wherein the first dielectric core ( Fig. 8: VI ) is separated from the second dielectric core ( Fig. 8: UVI ) by the bottom cover portion ( Fig. 8: CP ).
Regarding claim 30, Jung teaches the memory device of claim 21 ( as discussed above), wherein a top surface of the bottom cover portion ( Fig. 7: CP ) is below a top surface of the first channel layer ( Fig. 7: VS ).
Regarding claim 31, Jung teaches a three-dimensional memory device ( [0034] The semiconductor device 1100 may be a nonvolatile memory device (e.g., a NAND FLASH memory device)), comprising: a plurality of stacked layers ( Fig. 7 EL and ILD; [0067] The electrode structure ST may include electrodes EL and insulating patterns ILD, which are alternately stacked in a direction perpendicular to the top surface of the lower semiconductor layer #100 ); a storage channel structure ( Fig. 7: VS ; [0151] The vertical structure VS may include a data storage layer, a channel layer, a gapfill insulating layer, a pad, and so forth ) vertically penetrating the stacked layers ( as shown in Fig. 7 ) and comprising a first channel layer ( Fig. 7: channel hole CH; [0070] Each of the vertical structures VS may be provided in channel holes CH; which are formed to penetrate the electrode structure ST ) and a first dielectric core ( Fig. 8: VI ) horizontally surrounded by the first channel layer ( Fig. 8: VS ); a select gate structure ( Fig. 7: bit line BL ) on the plurality of stacked layers ( Fig. 7: ST ); and a select channel structure ( Fig. 7: UHL ) vertically penetrating the select gate structure ( Fig. 7: bit line BL ) and comprising a second channel layer ( Fig. 7: UCS ) and a second dielectric core ( Fig. 8: TL1 ) horizontally surrounded by the second channel layer ( Fig. 7: UCS ); wherein the first dielectric core ( Fig. 8: VI ) is separated from the second dielectric core ( Fig. 8: UVI ) by the second channel layer ( Fig. 8: UCS ), and a bottom surface of the second dielectric core ( Fig. 8: CP ) is lower than a top surface of the first channel layer ( as shown in Fig. 8 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 22 are rejected under U.S.C. 103 as being unpatentable over Jung et al; US 2023/0014037 A1; 03/2022 in view of Jung et al.; US 2021/0202458 A1; 12/2019.
Claim 2: Jung (037) discloses the memory device of claim 1 (as discussed above).
Jung (037) does not appear to disclose a distance between adjacent two first channel layers is less than a distance between adjacent two second channel layers.
However, Jung (458) teaches a distance ( Fig. 3 distance between #132 columns in region II ) between adjacent two first channel layers ( [0069] The vertical structure #132 may include a core region #138, a channel layer #136, a dielectric structure #134, and a pad pattern #140) is less than a distance ( Fig. 3 distance between #132 columns in region I ) between adjacent two second channel layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jung (458) with Jung (037) to implement a distance between adjacent two first channel layers is less than a distance between adjacent two second channel layers because of the need to minimize broadside coupling and the desire to maintain signal integrity for high-speed signals.
Claim 22: Jung (037) discloses the memory device of claim 21 (as discussed above).
Jung (037) does not appear to disclose a distance between adjacent two first channel layers is less than a distance between adjacent two second channel layers.
However, Jung (458 ) teaches a distance ( Fig. 3 distance between #132 columns in region II ) between adjacent two first channel layers ( [0069] The vertical structure #132 may include a core region #138, a channel layer #136, a dielectric structure #134, and a pad pattern #140) is less than a distance ( Fig. 3 distance between #132 columns in region I ) between adjacent two second channel layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jung (458) with Jung (037) to implement a distance between adjacent two first channel layers is less than a distance between adjacent two second channel layers because of the need to minimize broadside coupling and the desire to maintain signal integrity for high-speed signals.
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Jung et al; US 2023/0014037 A1; 03/2022 in view of Kim et al.; US 2023/0186990 A1; 07/2022.
Claim 3: Jung discloses the memory device of claim 1 (as discussed above).
Jung does not appear to disclose the second channel layer extends into the storage channel structure, and further in contact with a top surface of a first dielectric core of the storage channel structure.
However, Kim teaches the second channel layer ( [0065] second vertical channel structures VS2 ) extends into the storage channel structure ( [0084] Each of the first to third vertical channel structures VS1, VS2, and VS3 may include a data storage pattern DSP ), and further in contact with a top surface of a first dielectric core ( [0085] The vertical semiconductor pattern VSP may be provided between the data storage pattern DSP and the gapfill insulating pattern VI ) of the storage channel structure ( [0084] a data storage pattern DSP).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Jung to implement the second channel layer extends into the storage channel structure, and further in contact with a top surface of a first dielectric core of the storage channel structure because this approach would improve electrical connectivity and device reliability.
Allowable Subject Matter
Claim 32 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817