DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 14, 2026 has been entered.
Response to Amendment
The Amendment filed January 14, 2026 has been entered. Claims 1-7 and 9-21 are pending in the application.
Response to Arguments
Applicant’s arguments , see pages 7-9 of Remarks filed January 14, 2026 with respect to the rejection of claims 1-7 and 9-21 under 35 U.S.C. § 102 (a)(1) and 35 U.S.C. § 103 have been fully considered in view of the Amendment and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of previously cited references.
Claim Objections
Claim 3 is objected to because of the following informalities: “the first channel” should be “the first channel layer” to avoid indefiniteness and lack of antecedent basis. The “the first channel” has been interpreted as “the first channel layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-6, 9-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung; Euntaek et al. (US 2024/0081064; hereinafter Jung) in view of Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu).
Regarding claim 1, Jung discloses a three-dimensional memory device, comprising:
a storage channel structure (CH1; Figs 2,4C, ¶ [0030-76]) vertically penetrating a plurality of stacked layers (120,130; Figs 2,4C; ¶ [0035-37]) and comprising a first channel layer (140,145; Figs 2,4C; ¶ [0038-39,0041]) and a first dielectric core (144; Figs 2,4C; ¶ [0038-39]) horizontally surrounded by the first channel layer;
a select gate structure (150,192,193; Figs 2,4C; ¶ [0051-53]) on the plurality of stacked layers; and
a select channel structure (CH2; Figs 2,4C, ¶ [0057-59]) penetrating the select gate structure and comprising:
a block layer (172; Figs 2,4C, ¶ [0061]) in contact with the select gate structure,
a semiconductor spacer layer (171; Figs 2,4C, ¶ [0061-63]) covering the block layer,
a second channel layer (170; Figs 2,4C, ¶ [0060-63]) in contact with the insulating layer and the first channel layer (as shown in Fig 4C and associated description, 170 is in contact with 145,140 through 191C {¶ [0045,0057]}) and
a second dielectric core (174; Figs 2,4C, ¶ [0059-60]) horizontally surrounded by the second channel layer and separated from the first dielectric core (as shown in Fig 4C), wherein a second lateral size of a bottom surface of the second dielectric core (174) is that than a first lateral size of a top surface of the first dielectric core (144, as is depicted in Fig 4C).
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Jung does not disclose that the semiconductor spacer layer 171 is an insulating layer. However, Jung discloses that the semiconductor spacer layer 171 may be replaced with a separate spacer layer other than a semiconductor (¶ [0063]).
In the same field of endeavor, Ryu discloses a related memory device, select gate structure (SSL; Figs 3,9B; ¶ [0051,0056,0077]); and select channel structure (VS_U; Figs 2-3, ¶ [0077-79]), the select channel structure comprising:
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a select channel structure (VS_U; Figs 2-3, ¶ [0077-79]) penetrating the select gate structure and comprising:
a block layer (126,132d,121; Figs 3,9B; ¶ [0063,109, 0125-126,0115]) in contact with the select gate structure,
an insulating layer (132e; Fig 9B; ¶ [0125]) covering the block layer,
a second channel layer (130_UV, 130_HC1; Fig 9B, ¶ [0087-89]) in contact with the insulating layer and the first channel layer (shown in Fig 9B) and
a second dielectric core (the portion of 134 above 130_HC12; Fig 9B, ¶ [0087-88]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC12).
Further, both Jung (for example, Figs 3,4A-B,4D-E) and Ryu (for example, Figs 5A-E,9A,11) disclose a variety of variants to the select channel structure, and such structures are well-known in the art. It would have been obvious to a person having ordinary skill in the art to have combined the insulating layer of Ryu with the select channel structure of Jung, by, for example, replacing the semiconductor spacer layer 171 of Jung with an insulating layer as taught by Ryu (perhaps following the use of 171 as an etch stop layer (Jung; ¶ [0063]). One may have been motivated to do this in order to provide an improved interface between the second channel layer (Jung; 170; Fig 4C) and the block layer (Jung; 172; Fig 4C), the block layer acting as a gate dielectric for a select transistor comprised of 150,172,171, and 170 (Jung; Fig 4C; corresponding to Ryu; Fig 9B; SSL,132d,132e,and 130_UV). It is well-known in the art for a gate dielectric to comprise a multi-layer stack, such as a high-k dielectric (Ryu; 132d; ¶ [0125-126]) and silicon dioxide (Ryu; 132e; ¶ [0125-126]) in order to take advantage of the different properties of each, as Ryu has done. Replacing the semiconductor spacer layer with an insulating layer would both (1) eliminate a semiconductor interface between the semiconductor 171 and the (semiconductor) channel 170 and improve a high-k gate dielectric (Jung; 172; ¶ [0061]) to channel interface, as would be known to a person having ordinary skill in the art. One would have had a reasonable expectation of success because of the similar structures and similar endeavors of Jung and Ryu.
Note: in the following dependent claim explanations, “171-ins” will be used to mean the insulating layer 171 of Jung in view of Ryu as explained above, which as replaced the semiconductor spacer layer 171 of Jung.
Regarding claim 2, Jung in view of Ryu discloses the memory device of claim 1, wherein the block layer (172; Figs 2,4C) comprises:
a first block portion extending horizontally and in contact with a sidewall of the second channel layer (as shown in Fig 4C, a first block portion extends horizontally beneath a horizontal portion of 171-ins and contacts a vertical portion of 170);
a second block portion extending vertically on a sidewall of the select gate structure (150; as shown in Fig 4C); and
a third block portion extending horizontally on a top surface of the select gate structure (150; as shown in Fig 4C).
Regarding claim 3, Jung in view of Ryu discloses the memory device of claim 1, wherein a top end of the first channel layer (140,145; Figs 2,4C) is in contact with a bottom end of the second channel layer (170; as shown in Fig 4C and associated description, 170 is in contact with 145,140 through 191C {¶ [0045,0057]}) and a portion of the insulating layer (171-ins; Figs 2,4C) is located between the first dielectric core and the second dielectric core (as shown in Fig 4C, at least a lower horizontal portion of 171-ins is therebetween).
Regarding claim 4, Jung in view of Ryu discloses the memory device of claim 1, wherein the block layer (172; Figs 2,4C) comprises silicon oxynitride (¶ [0061]).
Regarding claim 5, Jung in view of Ryu discloses the memory device of claim 1, wherein:
the plurality of stacked layers (120,130; Figs 2,4C) comprise a plurality of alternatively stacked first conductive layers (130; Figs 2,4C; ¶ [0035-37]) and first dielectric layers (120; Figs 2,4C; ¶ [0030-37]); and
the select gate structure (150,192,193; Figs 2,4C, ¶ [0051-52]) comprises a second conductive layer (150; Figs 2,4C, ¶ [0051-52]) and second dielectric layers (193 and 192 respectively; Figs 2,4C, ¶ [0053,0051]) attached on a top surface and a bottom surface of the second conductive layer;
wherein the first conductive layer and the second conductive layer have different materials (150 may include a material different from a material of the first gate electrodes 130; ¶ [0051]).
Regarding claim 6, Ryu in view of Ryu discloses the memory device of claim 5, wherein the second conductive layer (150; Figs 2,4C) comprises one of polysilicon, doped polysilicon, and metal silicide (at least polysilicon or a doped semiconductor; ¶ [0051])).
Regarding claim 9, Jung in view of Ryu discloses the memory device of claim 1, wherein the select channel structure (CH2; Figs 2,4C) further comprises: an electrode plug (175; Fig 4C; ¶ [0059,0064]) on the second dielectric core (174; Fig 4C) and horizontally surrounded by the second channel layer (175 is formed by filling an opening in 174, 174 being surrounded by the second channel layer 170; ¶ [0131]).
Regarding claim 10, Jung discloses a memory system (Fig 10; ¶ [0132-141]), comprising:
a three-dimensional memory device configured to store data (1100; Fig 10; ¶ [0134]) and comprising:
a storage channel structure (CH1; Figs 2,4C, ¶ [0030-76]) vertically penetrating a plurality of stacked layers (120,130; Figs 2,4C; ¶ [0035-37]) and comprising a first channel layer (140,145; Figs 2,4C; ¶ [0038-39,0041]) and a first dielectric core (144; Figs 2,4C; ¶ [0038-39]) horizontally surrounded by the first channel layer;
a select gate structure (150,192,193; Figs 2,4C; ¶ [0051-53]) on the plurality of stacked layers; and
a select channel structure (CH2; Figs 2,4C, ¶ [0057-59]) penetrating the select gate structure and comprising:
a block layer (172; Figs 2,4C, ¶ [0061]) in contact with the select gate structure,
a semiconductor spacer layer (171; Figs 2,4C, ¶ [0061-63]) covering the block layer,
a second channel layer (170; Figs 2,4C, ¶ [0060-63]) in contact with the insulating layer and the first channel layer (as shown in Fig 4C and associated description, 170 is in contact with 145,140 through 191C {¶ [0045,0057]}) and
a second dielectric core (174; Figs 2,4C, ¶ [0059-60]) horizontally surrounded by the second channel layer and separated from the first dielectric core (as shown in Fig 4C), wherein a second lateral size of a bottom surface of the second dielectric core (174) is that than a first lateral size of a top surface of the first dielectric core (144, as is depicted in Fig 4C); and
a memory controller (1220; Fig 10; ¶ [0140]) coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.
Jung does not disclose that the semiconductor spacer layer 171 is an insulating layer. However, Jung discloses that the semiconductor spacer layer 171 may be replaced with a separate spacer layer other than a semiconductor (¶ [0063]).
In the same field of endeavor, Ryu discloses a related memory device, select gate structure (SSL; Figs 3,9B; ¶ [0051,0056,0077]); and select channel structure (VS_U; Figs 2-3, ¶ [0077-79]), the select channel structure comprising:
a select channel structure (VS_U; Figs 2-3, ¶ [0077-79]) penetrating the select gate structure and comprising:
a block layer (126,132d,121; Figs 3,9B; ¶ [0063,109, 0125-126,0115]) in contact with the select gate structure,
an insulating layer (132e; Fig 9B; ¶ [0125]) covering the block layer,
a second channel layer (130_UV, 130_HC1; Fig 9B, ¶ [0087-89]) in contact with the insulating layer and the first channel layer (shown in Fig 9B) and
a second dielectric core (the portion of 134 above 130_HC12; Fig 9B, ¶ [0087-88]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC12).
Further, both Jung (for example, Figs 3,4A-B,4D-E) and Ryu (for example, Figs 5A-E,9A,11) disclose a variety of variants to the select channel structure, and such structures are well-known in the art. It would have been obvious to a person having ordinary skill in the art to have combined the insulating layer of Ryu with the select channel structure of Jung, by, for example, replacing the semiconductor spacer layer 171 of Jung with an insulating layer as taught by Ryu (perhaps following the use of 171 as an etch stop layer (Jung; ¶ [0063]). One may have been motivated to do this in order to provide an improved interface between the second channel layer (Jung; 170; Fig 4C) and the block layer (Jung; 172; Fig 4C), the block layer acting as a gate dielectric for a select transistor comprised of 150,172,171, and 170 (Jung; Fig 4C; corresponding to Ryu; Fig 9B; SSL,132d,132e,and 130_UV). It is well-known in the art for a gate dielectric to comprise a multi-layer stack, such as a high-k dielectric (Ryu; 132d; ¶ [0125-126]) and silicon dioxide (Ryu; 132e; ¶ [0125-126]) in order to take advantage of the different properties of each, as Ryu has done. Replacing the semiconductor spacer layer with an insulating layer would both (1) eliminate a semiconductor interface between the semiconductor 171 and the (semiconductor) channel 170 and improve a high-k gate dielectric (Jung; 172; ¶ [0061]) to channel interface, as would be known to a person having ordinary skill in the art. One would have had a reasonable expectation of success because of the similar structures and similar endeavors of Jung and Ryu.
Note: in the following dependent claim explanations, “171-ins” will be used to mean the insulating layer 171 of Jung in view of Ryu as explained above, which as replaced the semiconductor spacer layer 171 of Jung.
Regarding claim 11, Jung in view of Ryu discloses the memory system of claim 10, wherein the block layer (172; Figs 2,4C) comprises:
a first block portion extending horizontally and in contact with a sidewall of the second channel layer (as shown in Fig 4C, a first block portion extends horizontally beneath a horizontal portion of 171-ins and contacts a vertical portion of 170);
a second block portion extending vertically on a sidewall of the select gate structure (150; as shown in Fig 4C); and
a third block portion extending horizontally on a top surface of the select gate structure (150; as shown in Fig 4C).
Regarding claim 12, Jung in view of Ryu discloses the memory system of claim 10, wherein:
a portion of the insulating layer (171-ins; Figs 2,4C) is located between the first dielectric core (144; Figs 2,4C) and the second dielectric core (174; Figs 2,4C; as shown in Fig 4C, at least a lower horizontal portion of 171-ins is therebetween);
the plurality of stacked layers (120,130; Figs 2,4C) comprise a plurality of alternatively stacked first conductive layers (130; Figs 2,4C; ¶ [0035-37]) and first dielectric layers (120; Figs 2,4C; ¶ [0030-37]); and
the select gate structure (150,192,193; Figs 2,4C, ¶ [0051-52]) comprises a second conductive layer (150; Figs 2,4C, ¶ [0051-52]) and second dielectric layers (193 and 192 respectively; Figs 2,4C, ¶ [0053,0051]) attached on a top surface and a bottom surface of the second conductive layer;
wherein the first conductive layer and the second conductive layer have different materials (150 may include a material different from a material of the first gate electrodes 130; ¶ [0051]).
Regarding claim 13, Jung in view of Ryu discloses the memory system of claim 10, wherein the select channel structure (CH2; Figs 2,4C) further comprises: an electrode plug (175; Fig 4C; ¶ [0059,0064]) on the second dielectric core (174; Fig 4C) and horizontally surrounded by the second channel layer (175 is formed by filling an opening in 174, 174 being surrounded by the second channel layer 170; ¶ [0131]).
Regarding claim 21, Jung in view of Ryu discloses the memory system of claim 10, wherein the block layer comprises silicon oxynitride (Jung; 172 may be silicon oxynitride, a high-k dielectric, others ¶ [0061]; in the explanation under claim 10 for combining Ryu with Jung, the example included a high-k dielectric, however, silicon oxynitride is a higher-k dielectric than silicon oxide, as is known in the art, and may be chosen instead of a traditional “high-k” material for a particular application and/or performance need.)
Regarding claim 14, Jung discloses a method for forming a three-dimensional memory device, comprising:
forming a plurality of stacked layers (120,130; Figs 2,4C,9A-B; ¶ [0035-37,0099-101]);
forming a storage channel structure (CH1; Figs 2,4C, ¶ [0030-76,0099]) vertically penetrating the plurality of stacked layers, the storage channel structure comprising a first channel layer 140,145; Figs 2,4C; ¶ [0038-39,0041]) and a first dielectric core (144; Figs 2,4C; ¶ [0038-39]) horizontally surrounded by the first channel layer;
forming a select gate structure (150,192,193; Figs 2,4C,9D; ¶ [0051-53,0109-112]) on the plurality of stacked layers; and
forming a select channel structure (CH2; Figs 2,4C,9E-9K; ¶ [0057-59,0076,0113-129]) penetrating the select gate structure, the select channel structure comprising:
a block layer (172; Figs 2,4C, ¶ [0061]) in contact with the select gate structure,
a semiconductor spacer layer (171; Figs 2,4C, ¶ [0061-63]) covering the block layer,
a second channel layer (170; Figs 2,4C, ¶ [0060-63]) in contact with the insulating layer and the first channel layer (as shown in Fig 4C and associated description, 170 is in contact with 145,140 through 191C {¶ [0045,0057]}) and
a second dielectric core (174; Figs 2,4C; ¶ [0059-60]) horizontally surrounded by the second channel layer and separated from the first dielectric core (as shown in Fig 4C), wherein a second lateral size of a bottom surface of the second dielectric core (174) is that than a first lateral size of a top surface of the first dielectric core (144, as is depicted in Fig 4C).
Jung does not disclose that the semiconductor spacer layer 171 is an insulating layer. However, Jung discloses that the semiconductor spacer layer 171 may be replaced with a separate spacer layer other than a semiconductor (¶ [0063]).
In the same field of endeavor, Ryu discloses a related memory device, select gate structure (SSL; Figs 3,9B; ¶ [0051,0056,0077]); and select channel structure (VS_U; Figs 2-3, ¶ [0077-79]), the select channel structure comprising:
a select channel structure (VS_U; Figs 2-3, ¶ [0077-79]) penetrating the select gate structure and comprising:
a block layer (126,132d,121; Figs 3,9B; ¶ [0063,109, 0125-126,0115]) in contact with the select gate structure,
an insulating layer (132e; Fig 9B; ¶ [0125]) covering the block layer,
a second channel layer (130_UV, 130_HC1; Fig 9B, ¶ [0087-89]) in contact with the insulating layer and the first channel layer (shown in Fig 9B) and
a second dielectric core (the portion of 134 above 130_HC12; Fig 9B, ¶ [0087-88]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC12).
Further, both Jung (for example, Figs 3,4A-B,4D-E) and Ryu (for example, Figs 5A-E,9A,11) disclose a variety of variants to the select channel structure, and such structures are well-known in the art. It would have been obvious to a person having ordinary skill in the art to have combined the insulating layer of Ryu with the select channel structure of Jung, by, for example, replacing the semiconductor spacer layer 171 of Jung with an insulating layer as taught by Ryu (perhaps following the use of 171 as an etch stop layer (Jung; ¶ [0063]). One may have been motivated to do this in order to provide an improved interface between the second channel layer (Jung; 170; Fig 4C) and the block layer (Jung; 172; Fig 4C), the block layer acting as a gate dielectric for a select transistor comprised of 150,172,171, and 170 (Jung; Fig 4C; corresponding to Ryu; Fig 9B; SSL,132d,132e,and 130_UV). It is well-known in the art for a gate dielectric to comprise a multi-layer stack, such as a high-k dielectric (Ryu; 132d; ¶ [0125-126]) and silicon dioxide (Ryu; 132e; ¶ [0125-126]) in order to take advantage of the different properties of each, as Ryu has done. Replacing the semiconductor spacer layer with an insulating layer would both (1) eliminate a semiconductor interface between the semiconductor 171 and the (semiconductor) channel 170 and improve a high-k gate dielectric (Jung; 172; ¶ [0061]) to channel interface, as would be known to a person having ordinary skill in the art. One would have had a reasonable expectation of success because of the similar structures and similar endeavors of Jung and Ryu.
Note: in the following dependent claim explanations, “171-ins” will be used to mean the insulating layer 171 of Jung in view of Ryu as explained above, which as replaced the semiconductor spacer layer 171 of Jung.
Regarding claim 15, Jung in view of Ryu discloses the method of claim 14, wherein:
forming the plurality of stacked layers (120,130; Figs 2,4C,9A-B) comprises alternatively stacking a plurality of first conductive layers (130; Figs 2,4C; ¶ [0035-37,0099-101]) and first dielectric layers (120; Figs 2,4C; ¶ [0030-37,0099]); and
forming the select gate structure (150,192,193; Figs 2,4C,9D) comprises:
forming a lower second dielectric layer (192; Figs 2,4C, ¶ [0053,0051,0110]) on the plurality of stacked layers,
forming a second conductive layer (150; Figs 2,4C,9E ¶ [0051-52,0110]) on the lower second dielectric layer, and
forming an upper second dielectric layer (193; Figs 2,4C,9E ¶ [0051-52,0110]) on the second conductive layer;
wherein the first conductive layer and the second conductive layer have different materials (150 may include a material different from a material of the first gate electrodes 130; ¶ [0051]).
Regarding claim 16, Jung in view of Ryu discloses the method of claim 15, wherein forming the select channel structure (CH2; Figs 2,4C,9E-9K; ¶ [0057-59,0076,0113-129]) comprises:
forming a select channel hole (OP2; Fig 9E; ¶ [0113-114]) in the select gate structure (150,192,193; Figs 2,4C,9E));
forming the block layer covering a sidewall (172 {172’}; Figs 4C,{9G}; ¶ [0061,0120-121]) and a bottom surface of the select channel hole; and
forming the insulating layer (171-ins {171’}; Figs 4C,{9G}; ¶ [0062,0120-121]) covering the block layer.
Regarding claim 17, Jung in view of Ryu discloses the method of claim 16, wherein forming the block layer and the insulating layer comprise: forming an initial dielectric layer covering the sidewall and the bottom surface of the select channel hole oxidizing an exposed portion of the initial dielectric layer with a first thickness into the insulating layer; and oxidizing a remaining portion of the initial dielectric layer with a second thickness into the block layer.
However, this would have been an obvious method of replacing the semiconductor spacer layer 172 with an insulating layer to form 172-ins as explained under claim 14, in considering the disclosed structure and materials of the block layer (Jung; 172 {Ryu;132d}, comprising a high-k dielectric, {for example hafnium silicon oxide; Ryu; Fig 9B; ¶ [0125-126]}) and the insulating layer (172-ins; Ryu; 132e, comprising silicon oxide; Fig 9B; ¶ [0125-126]), as well as knowledge in the art of oxidation. It would have been known to a person of ordinary skill in the art that oxidation of the first material layer formed (the initial high-k dielectric) and the semiconductor spacer layer 172 (comprising silicon; Jung; ¶ [0063]) may result in the second material layer 172-ins/132e as a product of reaction. Accordingly, this would have been an obvious method of formation. One would have had a reasonable expectation of success because the materials and methods are well-known in the art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jung; Euntaek et al. (US 2024/0081064; hereinafter Jung) in view of Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu), with supporting reference Nakaki; Hiroshi (US 2014/0061767; hereinafter Nakaki).
Regarding claim 7, Jung in view of Ryu discloses the memory device of claim 6, wherein the second conductive layer (150; Figs 2,4C) may comprise a doped semiconductor (¶ [0051]), and further discloses that 150 may be doped polysilicon (Fig 9D; ¶ [0098,0111]), but does not disclose 150 comprises boron doped polysilicon; however, boron would have been an obvious dopant choice to a person having ordinary skill in the art because boron is a very common dopant for silicon, including for polysilicon used as the conductive layer in a select gate structure (see, for example, Nakaki; Figs 3A-B,12A-B; ¶ [0096]).
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 18-20, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a sacrificial layer covering the insulating layer, removing portions of the sacrificial layer, the insulating layer, and the block layer that are located on a bottom of the select channel hole to expose a first dielectric core of the storage channel structure; removing the sacrificial layer, and portions of the insulating layer, the block layer, and the first dielectric core to expose the first channel layer”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817