DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed May 6, 2026 has been entered. The Amendment to Claim 3 has overcome the objection, and the objection is hereby withdrawn. Claims 1-3, 5-7, 9-20, and 22-23 are pending in the application.
Response to Arguments
Applicant’s arguments , see pages 8-12 of Remarks filed May 6, 2026 with respect to the rejection of claims 1-7 and 9-17 and 21 under 35 U.S.C. § 103 have been fully considered in view of the Amendment and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of additional interpretations of previously cited references, in view of the Amendment, (in particular, in view of Figs 10-11 of Ryu, and interpretation of features 130_HC1, 121, 126 of Ryu). In additional, although claims 18-20 were previously indicated as having allowable subject matter if re-written in independent form, a new ground(s) of rejection is made below in view the Amendment and the above-mentioned features and consideration. Please see the claim rejections below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being clearly anticipated by Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu).
Regarding claim 1, Ryu discloses a three-dimensional memory device (in particular, Figs 10-11, 1-2; ¶ [0030-129, 0168-179]); and, entire document), comprising:
a storage channel structure (VS_B; Figs 2,10; ¶ [0077-79]) vertically penetrating a plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]) and comprising a first channel layer (130_BV1; Fig 11, ¶ [0087-89, 0127-128]) and a first dielectric core (the portion of 134 beneath 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the first channel layer;
a select gate structure (SSL; Figs 10,11; ¶ [0051,0056,0077, 0127-128]) on the plurality of stacked layers;
a select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) vertically penetrating the select gate structure and comprising:
an insulating layer (132_UGI; Fig 11; ¶ [0109]),
a second channel layer (130_UV, 130_HC1; Fig 11, ¶ [0087-89, 0127-128]) in contact with the insulating layer and the first channel layer (as shown in Fig 11; ¶ [0127-128]) and
a second dielectric core (the portion of 134 above 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC1),
wherein a second lateral size of a bottom surface of the second dielectric core is less than a first lateral size of a top surface of the first dielectric core (as shown in Fig 11; {¶ [0084]}), and a second projection of the second dielectric core in a horizontal plane is within a first projection of the first dielectric core in the horizontal plane (as shown in Fig 11, the portion of 134 above 130_HC1 is concentric with and has a smaller diameter than the portion of 134 below 130_HC1).
Regarding claim 2, Ryu discloses the three-dimensional memory device of claim 1, wherein the select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) comprises a block layer comprising:
a first block portion (126; Fig 11; ¶ [0052,0057]) extending horizontally and in contact with a sidewall of the second channel layer (at least in contact with a lateral sidewall of the 130_HC1 portion of the second channel layer);
a second block portion ({ the insulating layer of claim 1} 132_UGI; Fig 11; ¶ [0109]) extending vertically on a sidewall of the select gate structure; and
a third block portion (121; Fig 11; ¶ [0118]) extending horizontally on a top surface of the select gate structure.
Regarding claim 3, Ryu discloses the memory device of claim 1, wherein a top end of the first channel layer (130_BV1; Fig 11) is in contact with a bottom end of the second channel layer (130_UV, 130_HC1; Fig 11).
Claims 1, 5-6, and 14-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being clearly anticipated by Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu). (Second Interpretation)
Regarding claim 1 (Second Interpretation), Ryu discloses a three-dimensional memory device (in particular, Figs 10-11, 1-2; ¶ [0030-129, 0168-179]); and, entire document), comprising:
a storage channel structure (VS_B; Figs 2,10; ¶ [0077-79]) vertically penetrating a plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]) and comprising a first channel layer (130_BV1,130_HC1; Fig 11, ¶ [0087-89, 0127-128]) and a first dielectric core (the portion of 134 beneath 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the first channel layer;
a select gate structure (SSL,126,121; Figs 10,11; ¶ [0051,0056,0063,0077, 0127-128]) on the plurality of stacked layers;
a select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) vertically penetrating the select gate structure and comprising:
an insulating layer (132_UGI; Fig 11; ¶ [0109]),
a second channel layer (130_UV; Fig 11, ¶ [0087-89, 0127-128]) in contact with the insulating layer and the first channel layer (as shown in Fig 11; ¶ [0127-128]) and
a second dielectric core (the portion of 134 above 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC1),
wherein a second lateral size of a bottom surface of the second dielectric core is less than a first lateral size of a top surface of the first dielectric core (as shown in Fig 11; {¶ [0084]}), and a second projection of the second dielectric core in a horizontal plane is within a first projection of the first dielectric core in the horizontal plane (as shown in Fig 11, the portion of 134 above 130_HC1 is concentric with and has a smaller diameter than the portion of 134 below 130_HC1).
Regarding claim 5, Ryu discloses the memory device of claim 1 (Second Interpretation), wherein:
the plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]) comprise a plurality of alternatively stacked first conductive layers (GSL,WL, comprising metals; ¶ [0055]) and first dielectric layers (120,125); and
the select gate structure (SSL, 126,121; Figs 10,11) comprises a second conductive layer (SSL, comprising a semiconductor; ¶ [0056]) and second dielectric layers (126,121; Figs 10,11; ¶ [0063]) attached on a top surface and a bottom surface of the second conductive layer;
wherein the first conductive layer and the second conductive layer have different materials.
Regarding claim 6, Ryu discloses the memory device of claim 5, wherein the second conductive layer (SSL; Figs 10,11) comprises one of polysilicon, doped polysilicon, and metal silicide (polycrystal silicon; ¶ [0056]).
Regarding claim 14, Ryu discloses a method for forming a three-dimensional memory device (in particular, Figs 10-11, 1-2; ¶ [0030-129, 0168-179]); and, entire document), comprising:
forming a plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]);
forming a storage channel structure (VS_B; Figs 2,10; ¶ [0077-79]) vertically penetrating the plurality of stacked layers, the storage channel structure comprising a first channel layer (130_BV, 130_HC1; Fig 11, ¶ [0087-89, 0127-128]) and a first dielectric core (the portion of 134 beneath 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the first channel layer;
forming a select gate structure (SSL,126,121; Figs 10,11; ¶ [0051,0056,0077, 0127-128]) on the plurality of stacked layers;
forming a select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) vertically penetrating the select gate structure, the select channel structure comprising:
an insulating layer (132_UGI; Fig 11; ¶ [0109]),
a second channel layer (130_UV; Fig 11, ¶ [0087-89, 0127-128]) in contact with the insulating layer and the first channel layer (as shown in Fig 11; ¶ [0127-128]) and
a second dielectric core (the portion of 134 above 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC1),
wherein a second lateral size of a bottom surface of the second dielectric core is less than a first lateral size of a top surface of the first dielectric core (as shown in Fig 11; {¶ [0084]}), and a second projection of the second dielectric core in a horizontal plane is within a first projection of the first dielectric core in the horizontal plane (as shown in Fig 11, the portion of 134 above 130_HC1 is concentric with and has a smaller diameter than the portion of 134 below 130_HC1).
Regarding claim 15, Ryu discloses the method of claim 14, wherein:
forming the plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10) comprises alternatively stacking a plurality of first conductive layers (GSL,WL, comprising metals; ¶ [0055]) and first dielectric layers (120,125); and
forming the select gate structure (SSL,126,121; Figs 10,11) comprises:
forming a lower second dielectric layer (126; Figs 10,11; ¶ [0063]) on the plurality of stacked layers,
forming a second conductive layer (SSL, comprising a semiconductor material; Figs 10,11; ¶ [0056]) on the lower second dielectric layer, and
forming an upper second dielectric layer (121; Figs 10,11; ¶ [0063]) on the second conductive layer;
wherein the first conductive layer and the second conductive layer have different materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu).
Regarding claim 7, Ryu discloses the memory device of claim 5, wherein the second conductive layer (SSL; Figs 10,11) may comprise polysilicon doped with a p-type impurity, but does not disclose the p-type impurity comprises boron; however, this would have been obvious to a person having ordinary skill in the art because boron is a very common p-type dopant for silicon.
Regarding claim 16, Ryu discloses the method of claim 15, wherein forming the select channel structure (VS_U; Figs 2,10,26) comprises:
forming a select channel hole (CHH_U; Fig 26; ¶ [0170]) in the select gate structure (SSL; Fig 26).
Ryu does not disclose forming a block layer covering a sidewall and a bottom surface of the select channel hole; and, forming the insulating layer (132_UGI; Fig 11) covering the block layer.
However, in another embodiment, Ryu discloses that 132_UGI may comprise a block layer (132d; Fig 9B; ¶ [0125-126]) and an insulating layer (132e; Fig 9B; ¶ [0125]). It would have been obvious to have used Fig 9B configuration for the channel insulating film 132_UGI with the Fig 11 configuration for channel films 130_UV and 130_BVI connected by 130_HC1. One would have been motivated to do this as an alternate embodiment combination to satisfy or balance various design, performance and/or reliability requirements influenced by the gate dielectric stack of a memory device, known to those of ordinary skill in the art. One would have had a reasonable expectation of success because Ryu has disclosed that specific embodiments are exemplary only, and may be combined with one another (¶ [0188]). Further, while Ryu does not specifically disclose forming the block layer (132d; Fig 9B) covering a sidewall and a bottom surface of the select channel hole (CHH_U; Fig 26) and, forming the insulating layer (132e; Fig 9B) covering the block layer, this would have been obvious from the structures shown in Figs 9B and 26 to one of ordinary skill in the art because: it is clear that 132d,132e are formed subsequent to the formation of CHH_U of Fig 26, and that 132e would be formed to cover 132d within CCH_U, at least because 132d is seen to surround a lower corner of 132e, and 132d covers a sidewall of SSL in Fig 9B with its horizontal portion implying coverage of a bottom surface of CHH_U before additional processing included in Fig 9B.
Regarding claim 17, Ryu discloses the method of claim 16, but does not disclose wherein forming the block layer and the insulating layer comprise: forming an initial dielectric layer covering the sidewall and the bottom surface of the select channel hole; oxidizing an exposed portion of the initial dielectric layer with a first thickness into the insulating layer; and oxidizing a remaining portion of the initial dielectric layer with a second thickness into the block layer.
However, this would have been obvious in considering the disclosed structure and materials of the block layer (132d, comprising for example hafnium silicon oxide; Fig 9B; ¶ [0125-126]) the insulating layer (132e, comprising silicon oxide; Fig 9B; ¶ [0125-126]). It would have been known to a person of ordinary skill in the art that oxidation of the first material layer formed, 132d, may result in the second material layer 132e as a product of reaction. Accordingly, this would have been an obvious method of formation. One would have had a reasonable expectation of success because the materials and methods are well-known in the art.
Regarding claim 18, Ryu discloses the method of claim 16, forming the select channel structure further comprises: forming a sacrificial layer (sacrificial polysilicon; ¶ [0172]) covering the insulating layer, removing portions of the sacrificial layer, the insulating layer, and the block layer that are located on a bottom of the select channel hole to expose a first dielectric core of the storage channel structure (¶ [0173]); removing the sacrificial layer, and portions of the insulating layer, the block layer, and the first dielectric core to expose the first channel layer (130_BCL; ¶ [0174]); and forming the second channel layer in the select channel hole and in contact with the exposed first channel layer (¶ [0175]).
While each detail may not be specifically mentioned, the method of claim 18 is essentially disclosed and would have been obvious to a person having ordinary skill in the art in consideration of Figs 9B,11,26-27 and ¶ [0172-176] and well-known methods in the art.
Regarding claim 19, Ryu discloses the method of claim 18, forming the select channel structure further comprises: forming a second dielectric core (the portion of 134 above 130_HC12 which fills CHH_U; Figs 9B,26; ¶ [0176, 0087-88]) in the select channel hole (CHH_U) and horizontally surrounded by the second channel layer.
Claims 9-11, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu) in view of Jung; Euntaek et al. (US 2024/0081064; hereinafter Jung).
Regarding claim 9, Ryu discloses the memory device of claim 1, but does not disclose wherein the select channel structure (VS_U; Figs 2,10) further comprises: an electrode plug on the second dielectric core and horizontally surrounded by the second channel layer.
In the same field of endeavor, Jung discloses a similar memory device wherein a select channel structure (CH2; Fig 4B; ¶ [0057-59]) comprises an electrode plug (175; Fig 4B; ¶ [0059,0064]) on a second dielectric core (174; Fig 4B; ¶ [0059-60]) and horizontally surrounded by a second channel layer (170, surrounding a lower horizontal surface perimeter of 175; Fig 4B; ¶ [0030]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the plug of Jung with the memory device of Ryu to arrive at the limitation of claim 9. While the channel of Jung does not horizontally surround vertical sidewalls of the plug, such a configuration also would have been obvious at least as an equivalent alternate structure when combining with the memory device of Ryu, since the plug and channel of Jung may be formed from the same material (for example polysilicon; ¶ [0064,0060]), making the location of an interface between them functionally unimportant. One may have been motivated to include the plug of Jung in order to provide improved electrical connection (increased contact area) to the BL_PAD of Ryu (Fig 10; ¶ [0080]) in a manner to similar to the connection of 175 to 181 (Jung; Fig 4B) of Jung. One would have had a reasonable expectation of success because of the similar structures and materials of Ryu and Jung.
Regarding claim 10, Ryu discloses a memory system, comprising: a three-dimensional memory device (in particular, Figs 10-11, 1-2; ¶ [0030-129, 0168-179]); and, entire document) configured to store data and comprising:
a storage channel structure (VS_B; Figs 2,10; ¶ [0077-79]) vertically penetrating a plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]) and comprising a first channel layer (130_BV1; Fig 11, ¶ [0087-89, 0127-128]) and a first dielectric core (the portion of 134 beneath 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the first channel layer;
a select gate structure (SSL; Figs 10,11; ¶ [0051,0056,0077, 0127-128]) on the plurality of stacked layers;
a select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) vertically penetrating the select gate structure and comprising:
an insulating layer (132_UGI; Fig 11; ¶ [0109]),
a second channel layer (130_UV, 130_HC1; Fig 11, ¶ [0087-89, 0127-128]) in contact with the insulating layer and the first channel layer (as shown in Fig 11; ¶ [0127-128]) and
a second dielectric core (the portion of 134 above 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC1),
wherein a second lateral size of a bottom surface of the second dielectric core is less than a first lateral size of a top surface of the first dielectric core (as shown in Fig 11; {¶ [0084]}), and a second projection of the second dielectric core in a horizontal plane is within a first projection of the first dielectric core in the horizontal plane (as shown in Fig 11, the portion of 134 above 130_HC1 is concentric with and has a smaller diameter than the portion of 134 below 130_HC1).
Ryu does not disclose the memory system comprises a memory controller coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.
In the same field of endeavor, Jung discloses a memory system (Fig 10; ¶ [0132-141]), comprising a similar three-dimensional memory device (1100; Fig 10; ¶ [0134]), configured to store data; and
a memory controller (1220; Fig 10; ¶ [0140]) coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.
Accordingly, it would have been obvious to have combined the memory system of Jung with the memory device of Ryu. One would have been motivated to do this in order to provide a memory system utilizing Ryu’s memory device, and would have had a reasonable expectation of success because of the similar memory devices disclosed by Jung and Ryu.
Regarding claim 11, Ryu in view of Jung discloses the memory system of claim 10, wherein the select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) comprises a block layer comprising:
a first block portion (126; Fig 11; ¶ [0052,0057]) extending horizontally and in contact with a sidewall of the second channel layer (at least in contact with a lateral sidewall of the 130_HC1 portion of the second channel layer);
a second block portion ({ the insulating layer of claim 1} 132_UGI; Fig 11; ¶ [0109]) extending vertically on a sidewall of the select gate structure; and
a third block portion (121; Fig 11; ¶ [0118]) extending horizontally on a top surface of the select gate structure.
Regarding claim 13, Ryu in view of Jung discloses the memory system of claim 10, but does not disclose wherein the select channel structure (VS_U; Figs 2,10) further comprises: an electrode plug on the second dielectric core and horizontally surrounded by the second channel layer.
However, Jung discloses in the similar three-dimensional memory device wherein a select channel structure (CH2; Fig 4B; ¶ [0057-59]) comprises an electrode plug (175; Fig 4B; ¶ [0059,0064]) on a second dielectric core (174; Fig 4B; ¶ [0059-60]) and horizontally surrounded by a second channel layer (170, surrounding a lower horizontal surface perimeter of 175; Fig 4B; ¶ [0030]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the plug of Jung with the memory system of claim 10 to arrive at the limitation of claim 13. While the channel of Jung does not horizontally surround vertical sidewalls of the plug, such a configuration also would have been obvious at least as an equivalent alternate structure when combining with the memory device of Ryu, since the plug and channel of Jung may be formed from the same material (for example polysilicon; ¶ [0064,0060]), making the location of an interface between them functionally unimportant. One may have been motivated to include the plug of Jung in order to provide improved electrical connection (increased contact area) to the BL_PAD of Ryu (Fig 10; ¶ [0080]) in a manner to similar to the connection of 175 to 181 (Jung; Fig 4B) of Jung. One would have had a reasonable expectation of success because of the similar structures and materials of Ryu and Jung.
Regarding claim 20, Ryu discloses the method of claim 19, but does not disclose forming the select channel structure further comprises: removing an upper portion of the second dielectric core to form a recess; and forming an electrode plug in the recess and horizontally surrounded by the second channel layer.
In the same field of endeavor, Jung discloses a similar memory device wherein a select channel structure (CH2; Fig 4B; ¶ [0057-59]) comprises an electrode plug (175; Fig 4B; ¶ [0059,0064]) on a second dielectric core (174; Fig 4B; ¶ [0059-60]) and horizontally surrounded by a second channel layer (170, surrounding a lower horizontal surface perimeter of 175; Fig 4B; ¶ [0030]).
Jung does not disclose the method of forming the electrode plug; however, this would have been obvious to a person having ordinary skill in the art according to well-known methods in the art. It would have been obvious to have combined the plug of Jung with the method of Ryu to arrive at the limitation of claim 20. While the channel of Jung does not horizontally surround vertical sidewalls of the plug, such a configuration also would have been obvious at least as an equivalent alternate structure when combining with the memory device of Ryu, since the plug and channel of Jung may be formed from the same material (for example polysilicon; ¶ [0064,0060]), making the location of an interface between them functionally unimportant. One may have been motivated to include the plug of Jung in order to provide improved electrical connection (increased contact area) to the BL_PAD of Ryu (Fig 3; ¶ [0080]) in a manner to similar to the connection of 175 to 181 (Jung; Fig 4B) of Jung. One would have had a reasonable expectation of success because of the similar structures and materials of Ryu and Jung.
Claims 10, 12 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu; Hyo Joon et al. (US 2021/0313344; hereinafter Ryu) in view of Jung; Euntaek et al. (US 2024/0081064; hereinafter Jung). (Second Interpretation)
Regarding claim 10 (Second Interpretation), Ryu discloses a memory system, comprising: a three-dimensional memory device (in particular, Figs 10-11, 1-2; ¶ [0030-129, 0168-179]); and, entire document) configured to store data and comprising:
a storage channel structure (VS_B; Figs 2,10; ¶ [0077-79]) vertically penetrating a plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]) and comprising a first channel layer (130_BV1,130_HC1; Fig 11, ¶ [0087-89, 0127-128]) and a first dielectric core (the portion of 134 beneath 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the first channel layer;
a select gate structure (SSL,126,121; Figs 10,11; ¶ [0051,0056,0077, 0127-128]) on the plurality of stacked layers;
a select channel structure (VS_U; Figs 2,10; ¶ [0077-79, 0127-128]) vertically penetrating the select gate structure and comprising:
an insulating layer (132_UGI; Fig 11; ¶ [0109]),
a second channel layer (130_UV; Fig 11, ¶ [0087-89, 0127-128]) in contact with the insulating layer and the first channel layer (as shown in Fig 11; ¶ [0127-128]) and
a second dielectric core (the portion of 134 above 130_HC1; Fig 11, ¶ [0087-88, 0127-128]) horizontally surrounded by the second channel layer and separated from the first dielectric core (separated by 130_HC1),
wherein a second lateral size of a bottom surface of the second dielectric core is less than a first lateral size of a top surface of the first dielectric core (as shown in Fig 11; {¶ [0084]}), and a second projection of the second dielectric core in a horizontal plane is within a first projection of the first dielectric core in the horizontal plane (as shown in Fig 11, the portion of 134 above 130_HC1 is concentric with and has a smaller diameter than the portion of 134 below 130_HC1).
Ryu does not disclose the memory system comprises a memory controller coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.
In the same field of endeavor, Jung discloses a memory system (Fig 10; ¶ [0132-141]), comprising a similar three-dimensional memory device (1100; Fig 10; ¶ [0134]), configured to store data; and
a memory controller (1220; Fig 10; ¶ [0140]) coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.
Accordingly, it would have been obvious to have combined the memory system of Jung with the memory device of Ryu. One would have been motivated to do this in order to provide a memory system utilizing Ryu’s memory device, and would have had a reasonable expectation of success because of the similar memory devices disclosed by Jung and Ryu.
Regarding claim 12, Ryu discloses the memory system of claim 10 (Second Interpretation), wherein:
a portion of the insulating layer (132_UGI; Fig 11) is located between the first dielectric core and the second dielectric core (as shown in Fig 11, a portion of 132_UGI extends below a bottom surface of an upper portion of 134, between the upper portion and a top surface of the lower portion of 134);
the plurality of stacked layers (ST, comprising 120,125,GSL,WL; Fig 10; ¶ [0046, 0168-179]) comprise a plurality of alternatively stacked first conductive layers (GSL,WL, comprising metals; ¶ [0055]) and first dielectric layers (120,125); and
the select gate structure (SSL, 126,121; Figs 10,11) comprises a second conductive layer (SSL, comprising a semiconductor; ¶ [0056]) and second dielectric layers (126,121; Figs 10,11; ¶ [0063]) attached on a top surface and a bottom surface of the second conductive layer;
wherein the first conductive layer and the second conductive layer have different materials.
Regarding claim 23, Ryu discloses the memory system of claim 10, wherein the insulating layer (132_UGI; Fig 11) is in direct contact with the first channel layer (130_BV1,130_HC1) and the second channel layer (130_UV; Fig 11).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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