CTFR 18/090,407 CTFR 81546 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 2, 4-6, 8, 9, 11-13, 15, 16, 18, 19 and 21 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ji et al, US Patent Application Publication 2020/0227429 (as cited in previous Office Action) Regarding claim 1 Ji teaches an apparatus, comprising: a flash memory chip further comprising: two pillars 772 ; a polysilicon layer 738 a flash memory chip intersecting two pillars; and a self-aligned dielectric fill 790 that is disposed between the two pillars 768 and external to each of the two pillars. the self- aligned dielectric fill extending through a polysilicon layer, the two pillars having respective access transistors formed with the polysilicon layer, wherein the self-aligned dielectric fill is configured to electrically isolate the pillars ( figures 7J-7L ). Regarding claim 2, Ji teaches the pillars are two pillars of different blocks of the flash memory chip ( figure 7L, with the “different blocks” referencing that the pillars are in different location of the flash memory chip ). Regarding claim 4, Ji teaches the two pillars are not surrounded by the dielectric fill ( figure 7L ). Regarding claims 5-6, Ji teaches the respective electrodes 738 of the access transistors are formed with the polysilicon layer, wherein the access transistors are source-gate-drain transistors ( figure 7L ) Regarding claim 8, Ji teaches a solid state drive comprising: a host interface 872 [ 0127 ]; a controller 870 coupled to the host interface ( figure 8B ); a plurality of flash memory chips ( part of NAND die 862 ) coupled to the controller, at least one of the flash memory chips further comprising two pillars 772 ; a polysilicon layer 738 intersecting the two pillars; and a self-aligned dielectric fill 790 that is disposed between the two pillars 772 and external to each of the two pillars, the self-aligned dielectric fill extending through a polysilicon layer, the two pillars having respective access transistors formed with the polysilicon layer, wherein the self-aligned dielectric fill is configured to electrically isolate the two pillars ( figures 7J-7L ). Regarding claim 9, Ji teaches the two pillars are pillars of different blocks of the flash memory chip ( figure 7L, with the “different blocks” referencing that the pillars are in different location of the flash memory chip ). Regarding claim 11, Ji teaches the two pillars are not surrounded by the dielectric fill ( figure 7L ). Regarding claims 12-13, Ji teaches respective electrodes of the access transistors are formed with the polysilicon layer, wherein the access transistors are source-gate-drain transistors. Regarding claim 15, Ji teaches a computer comprising: a plurality of processing cores ( GPU and processing core and other processing hardware or a combination, figure 10 ) [0139]; a main memory 1030 ; a memory controller 1022 coupled between the main memory and the plurality of processing cores; an I/O control hub 1060 coupled to the memory controller; an SSD 830 (Figure 8B) coupled to the I/O control hub, the SSD comprising i), ii) and iii) below: i) a host interface 872 [0127] ; ii) a controller 870, (figure 8B) coupled to the host interface; iii) a plurality of flash memory chips ( part of NAND die 860 ) coupled to the controller, at least one of the flash memory chips further comprising two pillars 772 , a polysilicon layer 738 intersecting two pillars; and a self-aligned dielectric fill 790 that is disposed between the two pillars 772 and external to each of the two pillars, the self- aligned dielectric fill extending through a polysilicon layer 738 the two pillars having respective access transistors formed with the polysilicon layer, wherein the self-aligned dielectric fill is configured to electrically isolate the two pillars ( figures 7J-7L ). . Regarding claim 16, Ji teaches the pillars are two pillars of different blocks of the flash memory chip ( figure 7L, with the “different blocks” referencing that the pillars are in different location of the flash memory chip ). Regarding claim 18, Ji teaches the pillars are not surrounded by the dielectric fill ( figure 7L ). Regarding claim 19, Ji teaches respective electrodes 738 of the access transistors are formed with the polysilicon layer ( figure 7L ). Regarding claim 21, Ji teaches the polysilicon layer 738 is separated by the self- aligned dielectric fill to form two distinct polysilicon portions, and the two pillars have respective access transistors formed with the two distinct polysilicon portions of the polysilicon layer ( figure 7L ) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3, 10, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al, US Patent Application Publication 2020/0227429 (as cited in previous Office Action) Regarding claims 3, 10 ,and 17, Ji fails to teach the self-aligned dielectric fill has a width greater than a spacing between neighboring pillars. However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) . 07-22-aia AIA Claim (s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji as applied to claim s 1, 2, 4-6, 8, 9, 11-13, 15, 16, 18, and 19 above, and further in view of Simsek-Ege et al, US Patent 8,969,948 (as cited in previous Office Action) Regarding claims 7, 14, and 20, Ji teaches, the polysilicon layer 738 is between a first layer 742 and a second layer 734 and the self-aligned dielectric fill extends through the first layer and the polysilicon layer and ends at the second layer ( figure 7L ) Ji fails to teach the first layer is a nitride layer and the second layer is an oxide layer. However, Simsek-Ege teaches that oxide and nitride are generally-used in the art as insulation layers. Figure 5A teaches that the first layer 517 is a cap layer made of a nitride, as a barrier layer and the second layer 503 as an oxide layer, which also acts as a barrier layer between the gate and the (source/drain region) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Simsek-Ege with that of Ji because oxide and nitride are generally-used in the art as insulation barrier layers . Response to Arguments 07-37 AIA Applicant's arguments filed 29 January 2026 have been fully considered but they are not persuasive. In response to Applicant’s argument that the cited prior art of Ji fails to teach the amended limitation of “a self-aligned dielectric fill that is disposed between two pillars and external to each of the two pillars…wherein the self-aligned dielectric fill is configured to electrically isolate the two pillars”, Examiner maintains that the reference of Ji still meets the limitation of this claim. Ji teaches the two pillars as channel 772. The dielectric fill 790 is disposed the two pillars 772 and are external to the two pillars since channel 772 doesn’t touch 772 in figure 7L. Further, since dielectric fill 790 is between two pillars 772, it would be an inherent feature that the dielectric fill would be configured to electrically isolate the two pillars. Therefore, the rejection of independent claim 1 under 35 USC 102(a)(1) using the cited prior art of Ji is maintained. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. 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QVJ /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/090,407 Page 2 Art Unit: 2899 Application/Control Number: 18/090,407 Page 3 Art Unit: 2899 Application/Control Number: 18/090,407 Page 4 Art Unit: 2899 Application/Control Number: 18/090,407 Page 5 Art Unit: 2899 Application/Control Number: 18/090,407 Page 6 Art Unit: 2899 Application/Control Number: 18/090,407 Page 7 Art Unit: 2899 Application/Control Number: 18/090,407 Page 8 Art Unit: 2899 Application/Control Number: 18/090,407 Page 9 Art Unit: 2899 Application/Control Number: 18/090,407 Page 10 Art Unit: 2899 Application/Control Number: 18/090,407 Page 11 Art Unit: 2899
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