DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 August 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-7, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pekny, US Patent Application Publication 2015/0348989.
Regarding claim 1 Pekny teaches an apparatus, comprising:
a flash memory chip further comprising:
two pillars 270,
a polysilicon layer 258/279 intersecting two pillars; and
a self-aligned dielectric fill 276 that is disposed between the two pillars and external to the body of each of the two pillars. the self- aligned dielectric fill extending through a polysilicon layer, the two pillars having respective access transistors formed with the polysilicon layer, wherein the self-aligned dielectric fill is configured to electrically isolate the pillars (figures 2C).
Figure 2 of Pekny fails to teach each pillar having a cylindrical body. However, figure 4 of Pekny teaches that polysilicon pillars 230 may have a cylindrical body, which is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that polysilicon pillars 270 of figure 2C may also be cylindrical, as it is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
Regarding claim 2, Pekny teaches the pillars are two pillars of different blocks of the flash memory chip (figure 2C, with the “different blocks” referencing that the pillars are in different location of the flash memory chip).
Regarding claim 4, Pekny teaches the two pillars are not surrounded by the dielectric fill (figure 2C)
Regarding claims 5-6, Pekny teaches the respective electrodes 279 of the access transistors are formed with the polysilicon layer, wherein the access transistors are source-gate-drain transistors (figure 2C)
Regarding claim 7, Pekny teaches the polysilicon layer 258/279 is between a nitride layer 262 [0037] and an oxide layer 252 [0036] and the self-aligned dielectric fill extends through the nitride layer and the polysilicon layer and ends at the oxide layer (figure 2C).
Regarding claim 21, Pekny teaches the polysilicon layer 258 is separated by the self- aligned dielectric fill to form two distinct polysilicon portions, and the two pillars have respective access transistors formed with the two distinct polysilicon portions of the polysilicon layer (figure 2C).
Claim(s) 8, 9, 11-16, and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pekny, US Patent Application Publication 2015/0348989 (newly submitted) in view of
Regarding claim 8, Pekny teaches a solid-state drive comprising:
A controller (part of processor 130, [0015])
a flash memory chips 100 coupled to the controller, at least one of the flash memory chips further comprising
two pillars 270;
a polysilicon layer 258/279 intersecting the two pillars; and
a self-aligned dielectric fill 276 that is disposed between the two pillars and external to each of the two pillars, the self-aligned dielectric fill extending through a polysilicon layer, the two pillars having respective access transistors formed with the polysilicon layer, wherein the self-aligned dielectric fill is configured to electrically isolate the two pillars (figure 2C).
Figure 2 of Pekny fails to teach each pillar having a cylindrical body, as well as a host interface, with the controller coupled to the host interface and a plurality of flash memory chips. However, figure 4 of Pekny teaches that polysilicon pillars 230 may have a cylindrical body, which is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
However, figure 4 of Pekny teaches that polysilicon pillars 230 may have a cylindrical body, which is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that polysilicon pillars 270 of figure 2C may also be cylindrical, as it is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
Pekny fails to teach a host interface, with the controller coupled to the host interface and a plurality of flash memory chips.
However, Ji teaches a host interface 872 [0127] with the controller 870 coupled to the host interface (figure 8B). In addition, Ji teaches a plurality of flash memory chips (part of NAND die 862) coupled to the controller (figure 8B) as components that are commonly used in the art to form a complete electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ji with that of Pekny because it is generally-known in the art that solid state drives consist or more than one flash memory chips (or devices) and the host interface allows for connection between the solid state drive and other components, thereby allowing the electrical device to function with peripheral devices.
Regarding claim 9, Pekny teaches the two pillars are pillars of different blocks of the flash memory chip (figure 2C, with the “different blocks” referencing that the pillars are in different location of the flash memory chip).
Regarding claim 11, Pekny teaches the two pillars are not surrounded by the dielectric fill (figure 2C).
Regarding claims 12-13, Pekny teaches respective electrodes 279 of the access transistors are formed with the polysilicon layer, wherein the access transistors are source-gate-drain transistors (figure 2C)
Regarding claim 14, Pekny teaches the polysilicon layer 258/279 is between a nitride layer 262 [0037] and an oxide layer 252 [0036] and the self-aligned dielectric fill extends through the nitride layer and the polysilicon layer and ends at the oxide layer (figure 2C).
Regarding claim 15, Pekny teaches a computer comprising:
at least one of the flash memory chips 100 further comprising
two pillars 270,
a polysilicon layer 258/279 intersecting two pillars; and
a self-aligned dielectric fill 276 that is disposed between the two pillars and external to each of the two pillars, the self- aligned dielectric fill extending through a polysilicon layer the two pillars having respective access transistors formed with the polysilicon layer, wherein the self-aligned dielectric fill is configured to electrically isolate the two pillars (figure 2C).
Figure 2 of Pekny fails to teach each pillar having a cylindrical body, a plurality of processing cores, a main memory; a memory controller coupled between the main memory and the plurality of processing cores; an I/O control hub coupled to the memory controller; an SSD coupled to the I/O control hub, the SSD comprising i), ii) and iii) below: i) a host interface; ii) a controller coupled to the host interface; iii) a plurality of flash memory chips coupled to the controller.
However, figure 4 of Pekny teaches that polysilicon pillars 230 may have a cylindrical body, which is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that polysilicon pillars 270 of figure 2C may also be cylindrical, as it is a generally-known shape that is used in forming polysilicon pillars for a memory chip.
Pekny fails to teach a plurality of processing cores, a main memory; a memory controller coupled between the main memory and the plurality of processing cores; an I/O control hub coupled to the memory controller; an SSD coupled to the I/O control hub, the SSD comprising i), ii) and iii) below: i) a host interface; ii) a controller coupled to the host interface; iii) a plurality of flash memory chips coupled to the controller.
However, Ji teaches a completed electronic component which uses a plurality flash memory chip. Figure 8B of Ji teaches a plurality of processing cores (GPU and processing core and other processing hardware or a combination, figure 10) [0139]; a main memory 1030; a memory controller 1022 coupled between the main memory and the plurality of processing cores; an I/O control hub 1060 coupled to the memory controller; an SSD 830 (Figure 8B) coupled to the I/O control hub, the SSD comprising i), ii) and iii) below: i) a host interface 872 [0127]; ii) a controller 870, (figure 8B) coupled to the host interface; iii) a plurality of flash memory chips (part of NAND die 860) coupled to the controller.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ji with that of Pekny because it is generally-known in the art that solid state drives consist or more than one flash memory chips (or devices) and that a computer device requires several components in order to properly function.
Regarding claim 16, Pekny teaches the pillars are two pillars of different blocks of the flash memory chip (figure 2C, with the “different blocks” referencing that the pillars are in different location of the flash memory chip).
Regarding claim 19, Pekny teaches respective electrodes 279 of the access transistors are formed with the polysilicon layer (figure 2C)
Regarding claim 20, Pekny teaches the polysilicon layer 258/279 is between a nitride layer 262 [0037] and an oxide layer 252 [0036] and the self-aligned dielectric fill extends through the nitride layer and the polysilicon layer and ends at the oxide layer (figure 2C).
Allowable Subject Matter
Claims 3, 10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, 10, and 17, the prior art fails to anticipate or render obvious the claimed invention including “...the self-aligned dielectric fill has a width greater than a spacing between neighboring pillars. ...” in combination with the remaining limitations. With regards to claims 3, 10, and 17, the cited prior art(s) of record teach all of the limitations presented, but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of these claims, either in anticipatory or in combination with other references.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 and 19-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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