CTNF 18/090,415 CTNF 100606 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-05 AIA Claim s 5, 7, 9, 11-14 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2026-04-20 . Applicant's election with traverse of Species B in the reply filed on 2026-04-20 is acknowledged. The traversal is on the ground(s) that Applicant argues that the species are not so patentably distinct as to place an undue burden on the examiner. This is not found persuasive because a search for anyone one of the specific features of the species indicated in the restriction made 2026-02-20 would not include the features of the other species thus a search burden is imposed on the examiner as every individual species would require a separate search and consideration. The requirement for the species restriction is still deemed proper and is therefore made FINAL. Applicant argues, with regards to the process claims that claim 1 is generic and encompasses each of the identified species and therefore should be examined. The examiner agrees, process (method) claims 1-4, 6, 8 and 10 which are generic OR directed toward the Elected species B have been rejoined and will be fully examined. Claim 18 has been withdrawn from consideration as it is directed toward Species D, E or C as it contains limitations requiring a thermal sensor or magnetic sensor, which are sensors that can perform the function required of the Species indicated . Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 states “wherein generating the signal is performed by the probe tip…” in lines 1-2. It is unclear from the Figure and specification how a probe tip can generate a signal. Claim 1 states that the signal is generated at the device under test and Fig 6 shows and AC bias voltage applied to the device under test which appears to be the signal generated, from which the probe tip measures said signal. For the purposes of compact prosecution, the examiner will interpret this claims such that a prior art that has a probe tip to measure a signal on a device under test shall be sufficient to read on the claim. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 6, 15-17, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Yoshida et al. (WO-2022219695-A1 – Refer to US-20240128047-A1 for English translation and references cited) . Regarding Claim 1, Yoshida teaches a method for fault isolation in integrated circuits using one or more probe tips, the method comprising: generating a signal at a circuit device under test (Fig 2: sample, 11) while a probe tip (Fig 2: probe, 10a & 10b) electrically interacts with a transistor or wire (Fig 2: conductor, 11a & 11b) of the circuit device under test (Paras [0043] and [0045] teach a signal is generated at the sample, 11, and that a potential difference is measured by the probes); detecting, based on the signal, an electrical output of the circuit device under test (Para [0045] teaches an output signal applied to controller, C1); and identifying, based on the electrical output, a location of a fault in or around the circuit device under test (Para [0047] teaches the fault spots can be specified based on the output). Regarding Claim 2, Yoshida teaches The method of claim 1, wherein the probe tip is connected to an electron beam (e-beam probe) (Can be seen in Fig 2, probes 10a/b are electrically connected to the entire apparatus including the device for generating the electron beam, EB1). Regarding Claim 3, Yoshida teaches The method of claim 1, wherein generating the signal is performed by the probe tip while the probe tip is in contact with the circuit device under test at or near a transistor (Paras [0043] and [0045] teaches the signal is measured by the probes, Para [0041] teaches the sample may contain transistors). Regarding Claim 4, Yoshida teaches The method of claim 1, wherein detecting the electrical output is performed by the probe tip while the probe tip is in contact with the circuit device under test at or near the transistor (Paras [0043] and [0045] teaches the signal is measured by the probes, Para [0041] teaches the sample may contain transistors). Regarding Claim 6, Yoshida teaches The method of claim 1, wherein identifying the fault location is based on e-beam absorbed current (EBAC) (Paras [0045] and [0047] teach using EBAC for identifying the fault). Regarding Claim 15, Yoshida teaches a device for fault isolation in integrated circuits using a probe tip, the device configured to: detect, based on a signal generated at a circuit device under test (Fig 2: sample, 11 | Paras [0043] and [0045] teach a signal is generated at the sample, 11, and that a potential difference is measured by the probes) while a probe tip (Fig 2: probe, 10a & 10b) is electrically interacts with the circuit device under test, an electrical output of the circuit device under test (Para [0045] teaches an output signal applied to controller, C1); and identify, based on the electrical output, a location of a fault at the circuit device under test Para [0047] teaches the fault spots can be specified based on the output). Regarding Claim 16, Yoshida teaches The device of claim 15, wherein the probe is connected to an electron beam (e-beam) probe (Can be seen in Fig 2, probes 10a/b are electrically connected to the entire apparatus including the device for generating the electron beam, EB1). Regarding Claim 17, Yoshida teaches The device of claim 15, wherein to identify the location is based on e-beam absorbed current (EBAC) (Paras [0045] and [0047] teach using EBAC for identifying the fault). Regarding Claim 20, Yoshida teaches a system for fault isolation in integrated circuits using a probe tip, the system comprising: a probe comprising a probe tip (Fig 2: probe, 10a & 10b - the probe tip being the end of the probe in contact with the sample, 11); and memory coupled to at least one processor (Para [0036] teaches memory contained within a computer), the at least one processor configured to (Paras [0034]-0036] teach the computer can give instructions to the controller): detect, based on a signal generated at a circuit device under test (Fig 2: sample, 11 | Paras [0043] and [0045] teach a signal is generated at the sample, 11, and that a potential difference is measured by the probes) while the probe tip (Fig 2: probe, 10a & 10b) electrically interacts with the circuit device under test, an electrical output of the circuit device under test (Paras [0043] and [0045] teach a signal is generated at the sample, 11, and that a potential difference is measured by the probes); and identify, based on the electrical output, a location of a fault at the circuit device under test (Para [0047] teaches the fault spots can be specified based on the output) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Tong et al. (WO-2019066802-A1) . Regarding Claim 8, Yoshida does not explicitly teach wherein identifying the location is based on a near-field fault isolation technique of laser assisted device alternation (LADA) or thermal assisted device alteration (TADA). However, Tong teaches wherein identifying the location is based on a near-field fault isolation technique of laser assisted device alternation (LADA) (Page 3 lns. 17-18 teaches that LADA is a known method for identifying faults). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of Yoshida to incorporate the technique of laser assisted device alternation of Tong. A motivation for this modification is LADA may temporarily alter transistor behavior to reveal faulty areas. Regarding Claim 19, Yoshida does not explicitly teach wherein to identify the location is based on a near-field fault isolation technique of laser assisted device alternation (LADA) or thermal assisted device alteration (TADA). However, Tong teaches wherein identifying the location is based on a near-field fault isolation technique of laser assisted device alternation (LADA) (Page 3 lns. 17-18 teaches that LADA is a known method for identifying faults). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device of Yoshida to incorporate the technique of laser assisted device alternation of Tong. A motivation for this modification is LADA may temporarily alter transistor behavior to reveal faulty areas . 07-21-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Sheiko et al. (Scanning Probe Microscopy of Polymers Volume 2 – Refer to NPL attached for references cited) . Regarding Claim 10, Yoshida teaches wherein the fault is an electrical open (Para [0047] teaches the fault may be an electrical open). Yoshida does not explicitly teach wherein identifying the location is based on a lock-in conductive atomic force microscopy (LI-CAFM) technique. However, Sheiko teaches wherein identifying the location is based on a LI-CAFM technique (Section 2.23.4.3 teaches using a lock-in amplifier with a conducting AFM probe). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method of Yoshida to include LI-CAFM technique. A motivation for this modification is this technique facilitates a simultaneous detection of the probe responses at several frequencies. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMIAH J BARRON whose telephone number is (571)272-0902. The examiner can normally be reached M-F 09:30-17:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEREMIAH J BARRON/Examiner, Art Unit 2858 /LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858 Application/Control Number: 18/090,415 Page 2 Art Unit: 2858 Application/Control Number: 18/090,415 Page 3 Art Unit: 2858 Application/Control Number: 18/090,415 Page 4 Art Unit: 2858 Application/Control Number: 18/090,415 Page 5 Art Unit: 2858 Application/Control Number: 18/090,415 Page 6 Art Unit: 2858 Application/Control Number: 18/090,415 Page 7 Art Unit: 2858 Application/Control Number: 18/090,415 Page 8 Art Unit: 2858
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