Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-18, 24, 26-27 and 30-32 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Youn (Pub. No.: US 2015/0228663) filed in the IDS on 12/28/2022.
Re claim 14, Youn, FIG. 16J teaches a memory device, comprising:
a semiconductor layer (502/504), a stacked structure ([553/554/556]/572) located on the semiconductor layer, and a dielectric layer (top most layer 572+776) covering the semiconductor layer and the stacked structure;
a channel hole (T31, FIG. 16A), penetrating through the stacked structure, wherein the channel hole comprises a channel structure (left 520, FIG. 16C, [0177]) disposed in a channel hole (T31, FIG. 16A) and extending through the stacked structure ([553/554/556]/572), wherein a polysilicon layer (736A, FIG. 16C, [0260]), a first metal silicide layer (736B, FIG. 16I, ¶ [0291]), and a through via contact metal layer (792) are sequentially stacked over an end of the channel structure (520) within the channel hole and are laterally in contact with the same dielectric layer (top most layer 572+776); and
a second metal silicide layer (704) and a first contact plug (582) extending through the dielectric layer (top most layer 572) in a region outside the stacked structure comprising interleaved gate lines (554) and isolation layers (572), wherein the second metal silicide layer (704) is located on the semiconductor layer (502/504), and the first contact plug (582) is located on the second metal silicide layer,
wherein the through via contact metal layer is configured to serve as a bit line contact plug (792, [0294]).
Re claim 15, Youn, FIG. 16J teaches the memory device of claim 14, wherein a diameter of the through via contact metal layer (diameter of the bottommost area of 792) is equal to a diameter of the polysilicon layer (736A).
Re claim 16, Youn, FIG. 16J teaches the memory device of claim 15, further comprising:
a second dielectric layer (776) located on the dielectric layer (top most layer 572+776); and
a bit line contact (794) located within the second dielectric layer (776), wherein the bit line contact is located on the through via contact metal layer (792), a diameter of the bit line contact (diameter of the bottommost portion of 792) is less than a diameter of the channel hole (T31 of FIG. 16A).
Re claim 17, Youn, FIG. 16J teaches the memory device of claim 16, wherein a thickness of the through via contact metal layer (vertical thickness of 792) is less than a thickness of the bit line contact (vertical thickness of 794).
Re claim 18, Youn, FIG. 16J teaches the memory device of claim 16, wherein a diameter of the bit line contact (792) is less than a diameter of the first contact plug (582).
Re claim 24, Youn, FIG. 16J teaches the memory device of claim 14, wherein the channel structure is a first channel structure; and the memory device further comprises:
a second channel structure (right 520) extending through the stacked structure (554/572); and
a gate line slit structure (504/704/582) comprising an array common source (504, [0176]), the gate line slit structure being arranged between the first channel structure (left 520) and the second channel structure (right 520).
Re claim 26, Youn, FIG. 16J teaches the memory device of claim 24, wherein the array common source comprises a conductive layer (582); and a top surface of the conductive layer is lower than a top surface of the dielectric layer (top most layer 572+776).
Re claim 27, Youn, FIG. 16J teaches the memory device of claim 14, wherein the first metal silicide layer comprises at least one of nickel silicide, cobalt silicide, tantalum silicide, or titanium silicide (736B, [0291]).
Re claim 30, Youn, FIG. 16J teaches the memory device of claim 14, wherein a projection of the bit line contact plug (792) on the semiconductor layer covers a projection of a bit line contact (794), arranged within a second dielectric layer (792), on the semiconductor layer (502/504).
Re claim 31, Youn, FIG. 12C teaches the memory device of claim 14, wherein the channel structure comprising a charge storage layer (540, [0180]) and a channel layer (520) surrounding the charge storage layer; and the polysilicon layer (536, [0179]) is arranged over the channel layer and the charge storage layer.
Re claim 32, Youn, FIG. 12C teaches the memory device of claim 14, further comprising: a buffer oxide layer (532, [0178]); the channel structure (520) extends through the stacked structure (572/554) and the buffer oxide layer; and the first contact plug (582) is arranged outside the buffer oxide layer without extending through the buffer oxide layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of Chinese Patent No.: CN110797345 (hereinafter `345).
Youn teaches all the limitation of claim 16/14.
Youn fails to teach the limitation of claim 19/22.
`345, FIG. 23 teaches herein an end of the stacked structure has a staircase structure, the memory device further comprises:
a second contact plug (554), located in the dielectric layer (230), wherein the second contact plug is connected to a surface of a corresponding staircase structure, and
a diameter of the second contact plug (554) is greater than a diameter of the bit line contact (552) (claim 19).
wherein a top surface of the first contact plug (552) protrudes above a top surface of the dielectric layer (330/230) (claim 22).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of effectively forming contact plugs for the gate electrode as taught by `345, Background technique.
Claim(s) 23, 25 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of DAI (Pub. No.: US 2019/0096901).
Re claim 23/29/25, Youn teaches all the limitation of claim 14/24.
Youn fails to teach the limitation of claim 23/29/25.
DAI teaches wherein a top surface of the first contact plug (126+248, FIG. 2, ¶ [0060]) is higher than a top surface of the through via contact metal layer (238, [0059]) (claim 23).
wherein a sidewall of the polysilicon layer (226, FIG. 2, [0056]) is in direct contact with the dielectric layer (the dielectric layer immediately right below layer 244) (claim 29).
wherein the gate line slit structure (126+248) further comprises a third contact plug (250) arranged over the array common source (126); and a top surface of the third contact plug (250) is higher than a top surface of the through via contact metal layer (238) (claim 25).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing manufacturing flexibility as taught by DAI, [0003]-[0004].
Claim(s) 21, 28 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn in view of LAI (Pub. No.: US 2022/0320140).
Re claim 28, Youn teaches all the limitation of claim 14.
Youn fails to teach the limitation of claim 28.
LAI teaches wherein a diameter of the polysilicon layer (828, FIG. 19, [0042]) is equal to a diameter of the first metal silicide layer (451, [0041]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity by lowering the contact resistance as taught by LAI, [0002].
Re claim 33/21, Youn, FIG. 16J teaches a memory device, comprising:
a semiconductor layer (502/504),
a stacked structure (554/572) over the semiconductor layer, and a dielectric layer covering the semiconductor layer and the stacked structure;
a channel structure (520) disposed in a channel hole (T31, FIG. 16A) and extending through the stacked structure, wherein a polysilicon layer (736A), a first metal silicide layer (736B), and a through via contact metal layer (792) are sequentially stacked over a top of the channel structure within the channel hole and are laterally in contact with the same dielectric layer (top most layer 572+776); and
a second metal silicide layer (704) and a first contact plug (582) formed in the dielectric layer, wherein the second metal silicide layer (704) is located over the semiconductor layer (502/504), and the first contact plug (582) is located over the second metal silicide layer,
wherein the through via contact metal layer is configured to serve as a bit line contact plug (792, [0294]); and
a diameter of the through via contact metal layer (topmost surface of 792), and a diameter of the first metal silicide layer (736B) are equal (part of claim 21).
Youn fails to teach a diameter of the polysilicon layer and a diameter of the first metal silicide layer are equal (claim 33 and the rest of 21).
LAI teaches a diameter of the polysilicon layer (828, FIG. 19, [0042]), and a diameter of the first metal silicide layer (451, [0041]) are equal.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity by lowering the contact resistance as taught by LAI, [0002].
Response to Arguments
Applicant's arguments with respect to claim 14-19 and 21-33 on the remarks filed on 12/19/2025 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893