DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 2, 2026, has been entered.
Response to Amendment
Claims 1-17 were previously pending. Applicant’s amendment filed April 2, 2026, has been entered in full. Claims 1, 5 and 11 are amended. Claims 15-17 are cancelled. No new claims are added. Accordingly, claims 1-14 are now pending.
Response to Arguments
Applicant has cancelled claims 15-17 (Remarks filed April 2, 2026, hereinafter Remarks: Page 6). Accordingly, the previous rejections of these claims are withdrawn as moot.
Applicant traverses the previous rejections under 35 U.S.C. 103 (Remarks: Pages 6-8). Examiner respectfully disagrees.
Applicant first argues that “Ishikawa does not teach or suggest using the design file and the noisiness level to divide the image” (Remarks: Page 6). Applicant acknowledges par. [0013] of Ishikawa, but points to a division into blocks described at [0055] and argues that this is not based on a design file and noisiness level (Remarks: Page 6). Examiner respectfully disagrees. Par. [0013] clearly describes distinguishing different portions of an image based on a level of noisiness of corresponding pattern types found from a design file. While Ishikawa does state that such noisiness level determinations are usually performed for blocks (i.e., “sub-images”) (e.g., [0056]), this still falls within the scope of the claims. I.e., Ishikawa divides an image into different blocks, each block having a different level of noisiness depending on a kind of pattern indicated by a design file. For example, some blocks are memory cell blocks, some blocks are logic circuit blocks, etc. Thus, the division of the image in Ishikawa is within the scope of being based on noisiness levels and a design file.
Applicant next argues that replacing the variance taught by Ishikawa with a standard deviation would change the principle of operation of Ishikawa (Remarks: Pages 7-8). Examiner respectfully disagrees. As was pointed out in the Final Rejection (Page 13), “standard deviation is simply the square root of variance.” Taking the square root of the variance used by Ishikawa would not change the principle of operation of Ishikawa. For example, as also explained in the Final Rejection (Page 13), “a threshold corrected to be a multiple of the standard deviation (i.e., a multiple of the square root of variance), as taught by Gallarda, would meet Ishikawa’s criteria that the threshold increases as variance increases.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘Ishikawa’ (US 2007/0053580 A1) in view of ‘Gallarda’ (US 6,539,106 B1).
Regarding claim 1, Ishikawa teaches a system (e.g., Fig. 3; Note from [0043] that many components of Fig. 3 are the same as Fig. 1) comprising:
a semiconductor review system (see mapped components below) that includes:
a light source that generates a beam of light (e.g., [0005], “bright field inspection apparatus, which illuminates the surface of a sample from a vertical direction and captures the image of its reflected light, is employed”);
a stage configured to hold a semiconductor wafer in a path of the beam of light ([0008]-[0009], Figs. 1-3, stage 1 configured by holder 2 to hold semiconductor wafer sample 3 so that it can be imaged by imaging device 4; As noted above with respect to [0005], the sample is in the path of the beam of light so that it can be imaged); and
a detector that receives the beam of light reflected from the semiconductor wafer ([0010], Fig. 3, imaging device 4); and
a processor in electronic communication with the semiconductor review system (see Note Regarding Processor below), wherein the processor is configured to:
receive an image of the semiconductor wafer that is generated using the detector (e.g., [0010], Figs. 1 and 3, image signal is received from imaging device at difference detection unit 6);
divide the image of the semiconductor wafer into a plurality of segments based on noisiness levels and a design file corresponding to the semiconductor wafer (e.g., [0013], unit 7 divides the image into different portions – i.e., segments – based on the kind of pattern indicated in a design data file; For example, [0013] lists a memory cell portion, a logic circuit portion, a wiring portion, and an analog circuit portion; Note from, e.g., [0043] that the apparatus of Fig. 3 described by Ishikawa includes unit 7; Note from, e.g., [0056] that the different portions may be represented as blocks – i.e., sub-images or logical frames), wherein the segments each have a different level of noise (e.g., [0013], noise level differs across the image depending on the kind of pattern) such that a first segment has a first level of noise and a second segment has a second level of noise, wherein the second level of noise is higher than the first level of noise (e.g., [0013], “the noise level of a semiconductor pattern differs depending on the kind of the pattern …”);
determine a standard deviation of the noise for each of the segments using a difference image of the image and a reference image ([0044], Fig. 3, difference detection unit 6 detects a difference image between an inspection image [i.e., “the image”] and a reference image; e.g., [0045], Fig. 3, difference image is used by variance computing unit 21 to determine a variance; e.g., [0057], variance is a measurement of noise at least because noisier regions have higher variance; e.g., [0055], variance is used to correct threshold “on a segment-by-segment basis”; see Note Regarding Standard Deviation below);
apply a threshold to each of the segments (e.g., [0053], [0055]-[0056], Fig. 3, threshold determined by units 7 and 23 is applied at defect detection unit 8 to each of the segments), wherein the threshold is a multiple of the standard deviation (see Note Regarding Standard Deviation below), and wherein the threshold will be higher for the second level of noise than the first level of noise (e.g., [0053], “For example, the detection threshold value correction unit 23 may correct the detection threshold value calculated by the detection threshold value calculation unit 7 in such a manner as to increase the detection threshold value as the variance computed by the variance computing unit 21 increases.”; also see Note Regarding Standard Deviation below);
determine pixels in the image that include a defect after applying the threshold (e.g., [0013], “the defect detection unit 8 compares the gray level difference with the thus determined threshold value to judge whether or not the portion under inspection is a defect or not”); and
label the pixels outside the threshold as defects-of-interest (e.g., [0013], “for each portion that has been judged to be a defect, the defect detection unit 8 outputs defect information which includes defect parameters such as the position of the defect”), wherein the pixels that include one of the defects-of-interest are outside the threshold for the segment where the pixels are located (e.g., [0045], [0013], Fig. 3, defective pixels are outside the detection threshold, which has been corrected by unit 23 for the segment where the pixels are located).
Note Regarding Processor. Ishikawa provides a mostly functional description of its inspection algorithms that operate on data received from the semiconductor review system (e.g., the functional block diagram of Fig. 3). Ishikawa describes steps of its algorithm as being performed by various “unit[s]” (e.g., Fig. 3, units 5, 6, 7, 21, 23, and 8) and describes at least some of these units as “comput[ing]” (e.g., [0011], [0045]), but does not explicitly state that its inspection algorithm functions are performed by a processor.
However, it has been taken as admitted prior art that it is old and well-known in the art of image analysis to implement an image processing algorithm using a processor in electronic communication with a system that provides image data and configured to perform the image processing algorithm on the image data. Such computer implementation advantageously allows the algorithm to be performed quickly and efficiently.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to implement the image processing algorithm of Ishikawa using a processor in electronic communication with a system that provides image data and configured to perform the image processing algorithm on the image data so that the algorithm could advantageously be performed quickly and efficiently.
Note Regarding Standard Deviation. Ishikawa teaches calculating a variance for each of multiple segments and applying a threshold that is corrected based on the variance (e.g., [0053]). Ishikawa does not teach any specific way of correcting the threshold based on the variance. Instead, Ishikawa generally states that “the detection threshold value correction unit 23 may correct the detection threshold value calculated by the detection threshold value calculation unit 7 in such a manner as to increase the detection threshold value as the variance computed by the variance computing unit 21 increases.” ([0053]).
Ishikawa does not explicitly teach calculating a standard deviation, or that the threshold is a multiple of the standard deviation.
However, Gallarda does teach a similar semiconductor wafer inspection algorithm that sets defect detection thresholds as a multiple of a standard deviation (Paragraph beginning at line 49 of column 8).
Gallarda teaches that this standard-deviation-based thresholding approach is advantageous because it “avoids the need to set a fixed threshold”, fixed thresholds being “error-prone” (Col. 8, ln. 54-58).
As suggested by, for example, Gallarda’s brief listing of multiple statistics (e.g., Col. 8, ln. 49-51), one of ordinary skill in the art would have been familiar enough with statistics to recognize that standard deviation is simply the square root of variance. Furthermore, a threshold corrected to be a multiple of the standard deviation (i.e., a multiple of the square root of variance), as taught by Gallarda, would meet Ishikawa’s criteria that the threshold increases as variance increases.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the system of Ishikawa as applied above with the standard deviation calculation and threshold correction of Gallarda in order to improve the system with the reasonable expectation that this would result in a system that advantageously avoided the need to set a fixed threshold and did so in a manner that met Ishikawa’s criteria that the threshold increases as variance increases. This technique for improving the method of Ishikawa was within the ordinary ability of one of ordinary skill in the art based on the teachings of Gallarda.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Ishikawa and Gallarda to obtain the invention as specified in claim 1.
Regarding claim 2, Ishikawa in view of Gallarda teaches the system of claim 1, and Ishikawa further teaches that the processor is further configured to send instructions to inspect the semiconductor wafer at locations corresponding to the pixels outside the threshold (e.g., [0013], defect detection unit 8 outputs defect information including position of the defect; e.g., [0014], “the defect information is supplied to an automatic defect classifying (ADC) apparatus (not shown) to examine the portion that has been judged to be a defect in further detail”).
Regarding claim 3, Ishikawa in view of Gallarda teaches the system of claim 1, and Gallarda further teaches that the multiple of the standard deviation is equal for each of the segments (e.g., Col. 8, ln. 52, multiple is set as a constant (i.e., not variable) “two”, such that it would remain equal for each of multiple segments; also see, e.g., Figs. 23A-24, Col. 18, ln. 16-57, in array mode the inspection process is repeated 2490 for each of multiple cells/segments, the process including feature comparison and defect reporting at 2480 without any adjustment of feature comparison parameters, such as the standard deviation multiplier, for different cells/segments).
Regarding claim 4, Ishikawa in view of Gallarda teaches the system of claim 1, and Ishikawa further teaches that some of the segments have edges that encompass regions of the image with more of the noise than other of the segments (e.g., [0057], Figs. 4A-B, “these pattern edges contain much noise”).
Regarding claim 5, Examiner notes that the claim recites a method that is substantially the same as the method performed by the processor of the system of claim 1. The system of claim 1, including its processor, is obvious over Ishikawa in view of Gallarda (see above). Therefore, claim 5 is also rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa in view of Gallarda for substantially the same reasons as claim 1.
Regarding claim 6, Ishikawa in view of Gallarda teaches the method of claim 5, and Ishikawa further teaches inspecting the pixels outside the threshold (e.g., [0013], defect detection unit 8 outputs defect information indicating the image positions – i.e., pixels – outside the threshold as defects; e.g., [0014], the defect information is supplied to an automatic defect classifying (ADC) apparatus for inspection).
Regarding claim 7, Ishikawa in view of Gallarda teaches the method of claim 6, and Ishikawa further teaches imaging the semiconductor wafer at locations corresponding to the pixels using a semiconductor inspection system (See, e.g., the semiconductor review system mapped in the rejection of claim 1; Also see ADC in [0014]).
Regarding claim 8, Ishikawa in view of Gallarda teaches the method of claim 5, and Ishikawa further teaches imaging the semiconductor wafer to generate the image (See, e.g., the semiconductor review system mapped in the rejection of claim 1).
Regarding claim 9, Examiner notes that the claim recites limitations that are substantially the same as limitations recited in claim 3. The invention of claim 3 is obvious over Ishikawa in view of Gallarda (see above). Therefore, claim 9 is also rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa in view of Gallarda for substantially the same reasons as claim 3.
Regarding claim 10, Examiner notes that the claim recites limitations that are substantially the same as limitations recited in claim 4. The invention of claim 4 is obvious over Ishikawa in view of Gallarda (see above). Therefore, claim 10 is also rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa in view of Gallarda for substantially the same reasons as claim 4.
Regarding claim 11, Examiner notes that the claim recites a non-transitory computer-readable storage medium, comprising one or more programs for executing on one or more computing devices: a method that is substantially the same as the method of claim 5.
The method of claim 5 is obvious over Ishikawa in view of Gallarda (see above).
As explained with respect to claim 1, Ishikawa’s teachings focus on a functional description of its image processing method. Ishikawa does not explicitly teach implementing its method as a non-transitory computer-readable storage medium, comprising one or more programs for executing on one or more computing devices: the method.
However, it has been taken as admitted prior art that it is old and well-known in the art of image analysis to implement an image processing method as a non-transitory computer-readable storage medium, comprising one or more programs for executing on one or more computing devices: the method. Such computer implementation advantageously allows a method to be performed quickly and efficiently.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to implement the image processing method of Ishikawa in view of Gallarda as applied above as a non-transitory computer-readable storage medium, comprising one or more programs for executing on one or more computing devices: the method so that the method could advantageously be performed quickly and efficiently.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Ishikawa and Gallarda to obtain the invention as specified in claim 11.
Regarding claim 12, Examiner notes that the claim recites limitations that are substantially the same as limitations recited in claim 2. The invention of claim 2 is obvious over Ishikawa in view of Gallarda (see above). Therefore, claim 12 is also rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa in view of Gallarda for substantially the same reasons as claim 2.
Regarding claim 13, Examiner notes that the claim recites limitations that are substantially the same as limitations recited in claim 3. The invention of claim 3 is obvious over Ishikawa in view of Gallarda (see above). Therefore, claim 13 is also rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa in view of Gallarda for substantially the same reasons as claim 3.
Regarding claim 14, Examiner notes that the claim recites limitations that are substantially the same as limitations recited in claim 4. The invention of claim 4 is obvious over Ishikawa in view of Gallarda (see above). Therefore, claim 14 is also rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa in view of Gallarda for substantially the same reasons as claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GEOFFREY E SUMMERS whose telephone number is (571)272-9915. The examiner can normally be reached Monday-Friday, 7:00 AM to 3:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chan Park can be reached at (571) 272-7409. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GEOFFREY E SUMMERS/Examiner, Art Unit 2669