DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Response to Arguments
Applicant’s arguments, see Claim Rejections - 35 USC § 102 and § 103, filed 09/17/2025, with respect to the rejection(s) of claim(s) 1-12 & 20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as detailed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 9, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN 111370423A) [Hereinafter Zhang and Kang (US 2022/0102372) [Hereinafter Kang].
Regarding claim 1, Zhang teaches A semiconductor device, comprising:
a stack structure [fig. 10, stack structure 1, para 24] including a core region [fig. 3, storage array area 13, para 57] in which a plurality of channel structures [fig. 10, channel structure 15, para 57] are formed;
a semiconductor layer [fig. 10, semiconductor layer 3, para 55] located on one side of the stack structure (1) in a stacking direction [vertical direction] of the stack structure [fig. 10],
the channel structures (15) extending to the semiconductor layer (3) [fig. 10],
and projections of the semiconductor layer (3) and the channel structures (15) in a plane parallel to the stacking direction not overlapping [fig. 10 illustrates projections/layers not overlapping];
a first insulating layer [fig. 10, insulating layer 5/dielectric layer 53 , para 63/91] at least located on a first surface (upper surface) of the semiconductor layer (3) far away from the stack structure (1) [fig. 10];
and a first leading-out portion [fig. 10, conductive structure 4 & lead point 31, para 61] penetrating through a portion of the first insulating layer (5/53) corresponding to the core region [region 13 as shown in fig. 3] in the stacking direction [vertical direction] and being in contact with the semiconductor layer (3) [fig. 10].
Zhang fails to explicitly disclose the channel structures extending to the semiconductor layer and having a portion in the semiconductor layer that has a smaller cross section dimension than a remaining of the channel structure.
However, Kang teaches the channel structures [fig. 2C, channel structures CH, para 24] extending to the semiconductor layer [fig. 2C, conductive layer 13, para 2; wherein the layer may be polysilicon which is a semiconductor material] and having a portion in the semiconductor layer [fig. 2C; wherein the portion CH2 passes thru the semiconductor layer 13, para 25] that has a smaller cross section dimension than a remaining of the channel structure [fig. 2C; wherein the CH2 portion which passes thru the semiconductor layer 13 has a smaller cross section dimension than a remaining portion of the channel structure (CH1)].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the channel structures to extend into the semiconductor layer to enhance gate control and carrier mobility improving overall device performance by reducing trap density and enabling narrower channels for better gate coupling.
Regarding claim 2, Zhang/Kang teaches The semiconductor device of claim 1, wherein a material of the first leading-out portion (Zhang, 31/4) includes a metal and/or a metal alloy less than 10 g/cm3 in density [Zhang, para 62; wherein the material is aluminum which is less than 10 g/cm3 in density].
Regarding claim 3, Zhang/Kang teaches The semiconductor device of claim 2, wherein the material of the first leading-out portion (Zhang, 4/31) is aluminum [Zhang, para 62; wherein the material is aluminum].
Regarding claim 4, Zhang/Kang teaches The semiconductor device of claim 1, wherein depths of all the channel structures in the stacking direction are the same [Zhang, fig. 10 illustrates all channel structures (15) have the same depth].
Regarding claim 5, Zhang/Kang teaches The semiconductor device of claim 1, wherein the first surface (Zhang, upper surface of semiconductor layer 3) is a flat surface [Zhang, fig. 10 illustrates upper surface of layer 3 to be flat].
Regarding claim 9, Zhang/Kang teaches The semiconductor device according to claim 1, wherein:
the stack structure (Zhang, 1) further includes:
a periphery region [Zhang, fig. 3, through array region 2, para 60] on at least one side of the core region [Zhang, region 13 as shown in fig. 3],
and gate layers [Zhang, fig. 10, gate layers 11, para 55] and second insulating layers [Zhang, fig. 10, insulating layers 12, para 55] that are alternately stacked [Zhang, para 55] in the stacking direction (vertical direction) within the core region [Zhang, fig. 10],
and the semiconductor device further includes:
a word line connection portion [Zhang, fig. 10, channel contact 24, para 65] located in the periphery region (Zhang, region 2) and electrically connected with the gate layers [Zhang, fig. 10; wherein the channel contact 24 is electrically connected with the gate layers through the semiconductor layer 3 as noted in para 87],
and a second leading-out portion [Zhang, fig. 10, pad lead-out point 26, para 65] penetrating through the first insulating layer (Zhang, 5/53) in the stacking direction (vertical direction) and electrically connected with the word line connection portion (Zhang, 24) [Zhang, fig. 10],
the first insulating layer (Zhang, 5/53) at least partially covering sidewalls of the second leading-out portion (Zhang, 26) extending in the stacking direction (vertical direction) [Zhang, fig. 10].
Regarding claim 11, Zhang/Kang teaches The semiconductor device of claim 9,
wherein a material of the second leading- out portion (Zhang, 26) includes a metal and/or a metal alloy less than 10 g/cm3 in density [Zhang, para 65 notates, “ The pad lead-out point 26 may include a conductive material such as aluminum...” wherein aluminum has a density of approximately 2.7 g/cm3].
Regarding claim 12, Zhang/Kang teaches The semiconductor device of claim 9,
wherein the second leading-out portion is formed integrally [Zhang, fig. 10; wherein lead out portion (Zhang, 26) is a single piece.].
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Kang as applied to 1-5, 9, & 11-12 above and further in view of Hu et al. (CN109037226A) [Hereinafter Hu].
Regarding claim 6, Zhang/Kang teaches The semiconductor device of claim 1, wherein:
the semiconductor device further includes a gate line slit structures [Zhang, fig. 10, gate line slit 16, para 61] which penetrate through the stack structure (Zhang, 1) in the stacking direction (vertical direction) and extend in a first direction (z-direction into paper) perpendicular to the stacking direction (vertical direction) [Zhang, fig. 10],
and a portion of the first surface between the gate line slit structures is a flat surface [Zhang, fig. 10; wherein the upper surface of layer 3 is a flat surface],
the first leading-out portion (Zhang, 4/31) is located on the flat surface [Zhang, fig. 10].
Zhang/Kang fails to explicitly disclose the semiconductor device further includes a plurality of gate line slit structures which penetrate through the stack structure.
However, Hu teaches an analogous device which includes a plurality of gate line slit structures [fig. 5, gate line slit 103, “The plurality of channel pillars 110 are arranged in an array, which are located between the gate line slits 103.”] which penetrate through the stack structure [“…gate line slit 103 penetrating the gate stacked structure”].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise a plurality of gate line slit structures to separate the channel layers providing isolation preventing interference and enabling independent control of different sections of the memory array beneficial for operations like programming and erasing ultimately improving the performance and control of the device.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang, Kang, & Hu as applied to 6 above and further in view of Nagai (US 8628981) [Hereinafter Nagai].
Regarding claim 7, Zhang/Kang/Hu teaches The semiconductor device of claim 6.
the second direction (horizontal direction) is perpendicular to the first direction (z-direction into the paper) and the stacking direction (vertical y-direction).
Zhang/Kang/Hu fails to explicitly disclose wherein a width of the first leading-out portion in a second direction is 200 nm-1200 nm.
However, Nagai teaches an analogous device wherein a width of the contact hole [fig. 5S, contact hole 69t, para 113] has a width in the second direction (horizontal) of approximately 1000 nm which lies within the claimed invention range disclosed.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the width of the leading-out portion in a second direction to fall within the range of 200nm – 1200nm for a lower resistance due to current flowing through a larger cross-sectional area which improves performance by faster signal propagation for higher speeds.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Kang as applied to 1-5, 9, & 11-12 above and further in view of Chen et al. (US 2021/0013303) [Hereinafter Chen].
Regarding claim 8, Zhang/Kang teaches The semiconductor device of claim 1,
wherein the semiconductor layer further comprises:
a semiconductor layer [Zhang, fig. 8, semiconductor layer 32, para 87];
and a doped semiconductor layer [Zhang, fig. 8, semiconductor layer 33, para 87] located on a side of the semiconductor layer (Zhang, 32) far away from the stack structure (Zhang, 1) [Zhang, fig. 8],
and wherein each of the channel structures (Zhang, 15) extends to the semiconductor layer (Zhang, 32) [Zhang, fig. 10].
Zhang/Kang fails to explicitly disclose wherein the semiconductor layer comprises a non-doped semiconductor layer.
However, Chen teaches an analogous device wherein the semiconductor layer [fig. 5, semiconductor layers 580/582, para 95] comprises a non-doped semiconductor layer [580, para 95 discloses layer may be silicon] on a side of an doped semiconductor layer [fig. 5, 582, para 95].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the semiconductor layer to comprise a non-doped layer to reduce contact resistance leading to improved device performance and reliability.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Kang as applied to 1-5, 9, & 11-12 above and further in view of Wu et al. (CN111341774A) [Hereinafter Wu].
Regarding claim 10, Zhang/Kang teaches The semiconductor device of claim 9.
Zhang/Kang fails to explicitly disclose wherein an aspect ratio of the second leading-out portion is less than 1:4,
the aspect ratio is a ratio of a depth of the second leading- out portion in the stacking direction to a maximum width of a projection in a plane perpendicular to the stacking direction.
However, Wu teaches a leading-out portion [fig. 31, common source 601, para 152] wherein an aspect ratio is less than 1:4. Para 152 specifically states, “the ratio of the height of the first array common source 601 in the direction perpendicular to the first surface 37 (the D1 direction in the figure) to the width of the first array common source 601 in the direction parallel to the first surface 37 (the D2 direction in the figure) is (0.1-10):1. [0153] The present application can also make the ratio of the height to the width of the first array common source 601 satisfy (0.1-10):1, so as to prepare an array common source 60 structure with excellent structure near the bottom.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the aspect ratio of the lead out portion to be less than 1:4 for excellent structure and enabling optimal transmission of electrical signals as taught by Wu resulting in optimal performance of the device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang, Kang, & Liu (US 2020/0350287).
Regarding claim 20, Zhang teaches A memory system,
and a semiconductor device [fig. 10],
wherein: the semiconductor device [fig. 10], includes:
a stack structure [fig. 10, stack structure 1, para 24] including a core region [fig. 3, storage array area 13, para 57] in which a plurality of channel structures [fig. 10, channel structure 15, para 57] are formed;
a semiconductor layer [fig. 10, semiconductor layer 3, para 55] located on one side of the stack structure (1) in a stacking direction [vertical direction] of the stack structure [fig. 10],
the channel structures (15) extending to the semiconductor layer (3) [fig. 10],
and projections of the semiconductor layer (3) and the channel structures (15) in a plane parallel to the stacking direction not overlapping [fig. 10 illustrates projections/layers not overlapping];
a first insulating layer [fig. 10, insulating layer 5/dielectric layer 53 , para 63/91] at least located on a first surface (upper surface) of the semiconductor layer (3) far away from the stack structure (1) [fig. 10];
and a first leading-out portion [fig. 10, conductive structure 4 & lead point 31, para 61] penetrating through a portion of the first insulating layer (5/53) corresponding to the core region [region 13 as shown in fig. 3] in the stacking direction [vertical direction] and being in contact with the semiconductor layer (3) [fig. 10].
Zhang fails to explicitly disclose
a controller;
and the controller is coupled to the semiconductor device and used for controlling the semiconductor device to store data.
However, Liu teaches an analogous device comprising a controller [fig. 3, controller circuit 314, para 45] and the controller (314) is coupled to the semiconductor device [fig. 3, semiconductor structure 304, para 49] and used for controlling the semiconductor device to store data [para 45].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the memory system to comprise a controller to facilitate the operation of the memory device as taught by Liu through managing data flow and communication.
Zhang/Liu fails to explicitly disclose the channel structures extending to the semiconductor layer and having a portion in the semiconductor layer that has a smaller cross section dimension than a remaining of the channel structure.
However, Kang teaches the channel structures [fig. 2C, channel structures CH, para 24] extending to the semiconductor layer [fig. 2C, conductive layer 13, para 2; wherein the layer may be polysilicon which is a semiconductor material] and having a portion in the semiconductor layer [fig. 2C; wherein the portion CH2 passes thru the semiconductor layer 13, para 25] that has a smaller cross section dimension than a remaining of the channel structure [fig. 2C; wherein the CH2 portion which passes thru the semiconductor layer 13 has a smaller cross section dimension than a remaining portion of the channel structure (CH1)].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the channel structures to extend into the semiconductor layer to enhance gate control and carrier mobility improving overall device performance by reducing trap density and enabling narrower channels for better gate coupling.
Allowable Subject Matter
Claim 13-16, & 18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, Zhang teaches A fabrication method of a semiconductor device, comprising:
forming a first insulating layer [fig. 10, insulating layer 5/dielectric layer 53 , para 63/91] on one side of an intermediate semiconductor device,
wherein the intermediate semiconductor device includes a stack structure [fig. 10, stack structure 1, para 24] and a semiconductor layer [fig. 10, semiconductor layer 3, para 55] on one side of the stack structure in a stacking direction (vertical direction) of the stack structure (1) [fig. 10],
the stack structure includes a core region [fig. 3, storage array area 13, para 57] in which a plurality of channel structures are formed [fig. 10, channel structure 15, para 57],
the channel structures (15) extend to the semiconductor layer (3) [fig. 10], and projections of the semiconductor layer (3) and the channel structures (15) in a plane parallel to the stacking direction do not overlap [fig. 10 illustrates projections/layers not overlapping],
the first insulating layer (5/53) is at least formed on a first surface [upper surface] of the semiconductor layer (3) far away from the stack structure (1) [fig. 10];
and forming a first leading-out portion [fig. 10, conductive structure 4 & lead point 31, para 61] that penetrates through the first insulating layer (5/53) in the stacking direction (vertical direction) and is in contact with the semiconductor layer (3) in a portion of the first insulating layer (5) corresponding to the core region [fig. 3/10, storage array area 13 notated in fig. 3, para 57],
wherein before forming the first insulating layer (5) on the one side of the intermediate semiconductor device,
the fabrication method further comprises:
forming the intermediate semiconductor device [annotated fig. 10] based on an initial semiconductor device [annotated fig. 10],
wherein the initial semiconductor device includes a plurality of initial channel structures [fig. 10, conductive channels 73, para 68],
and a substrate [fig. 10, substrate 71, para 68].
Zhang fails to explicitly disclose the stack structure,
as well as a substrate insulating layer
and a substrate that are disposed in sequence in the stacking direction of the stack structure,
the initial channel structures penetrate through the stack structure and the substrate insulating layer in sequence
and extend into the substrate,
the channel structures includes portions of the initial channel structures in the stack structure.
However, Huang teaches the stack structure [fig. 4, alternating layers of 206/205, para 29],
as well as a substrate insulating layer [fig. 4, stop layer 210a, para 28]
and a substrate [fig. 4, substrate 200, para 27] that are disposed in sequence in the stacking direction of the stack structure,
the initial channel structures [fig. 4, layers 209/202/203/204, para 30] penetrate through the stack structure (205/206) [fig. 4] and the substrate insulating layer (210a) in sequence [fig. 4]
and extend into the substrate (200) [fig. 4],
the channel structures includes portions of the initial channel structures in the stack structure [wherein both the channel structures and initial channel structures comprise the storage layers (i.e. tunneling layer, blocking layer, and trapping layer].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise an initial semiconductor structure to increase storage capacity within a smaller footprint compared to traditional two-dimensional devices, and reducing latency by vertically stacking through shorter connection paths of memory cells resulting in improved performance and storage capacity.
Zhang/Huang teaches removing the substrate insulating layer (210a) [Huang, fig. 11] and the exposed portions of the initial channel structures (layers 202,203, & 204) [Huang, fig. 11].
Zhang/Huang fails to explicitly disclose removing the substrate to expose portions of the initial channel structures in the substrate;
and forming the semiconductor layer.
However, Kong teaches [para 35-36] wherein the substrate of a memory device may be removed to enable bonding of additional memory devices to form a higher density 3D memory device. Kong further details
and forming the semiconductor layer [fig. 1A-1C, semiconductor layer 108, para 38].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to remove the substrate to expose the initial channel structures in the substrate and form the semiconductor layer to enable further densification of the 3D memory device, which improves storage capacity enabling higher performance of the device.
The prior art made of record singularly and/or combined fails to explicitly disclose wherein the initial channel structures include sacrificial structures in the substrate and the substrate insulating layer, and channel structures in the stack structure,
wherein removing the substrate insulating layer and the exposed portions of the initial channel structures further comprises:
removing the substrate insulating layer and functional layers of the sacrificial structures to expose one side of the stack structure and channel layers of the sacrificial structures;
at least removing the channel layers and dielectric layers of the sacrificial structures to expose part of the channel structures;
and filling isolation insulating layers within second gaps surrounded by dielectric layers of the channel structures to enclose the second gaps.
Thereby claim 13 contains allowable subject in light of the additional limitations recited therein.
Claims 14-16 & 18 are allowable at least based upon their dependency on claim 13.
Conclusion
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812