DETAILED ACTION
This action is responsive to the application No. 18/090,471 filed on December 28, 2022.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention III, corresponding to product claims 12-25, in the reply filed on September 2, 2025, is acknowledged. Claims 1-11 are withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the:
two dimensional (2D) die…comprise a light sensitive pixel array, a superstrate attached to said one or more 2D die, a fluid deployed between said one or more 2D die and said product substrate, points on said one or more 2D-die, and points on said product substrate (claim 12);
wherein said 3D IC is an application specific integrated circuit (ASIC) system (claim 13);
wherein said 3D IC is a system-on-a chip (SoC) (claim 14);
a system designed using any of the following design approaches: a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation, a 3D logic implementation with a 2D memory implementation, and a 3D logic implementation with a 3D memory implementation (claim 16); and
wherein said imager is curved (claim 25),
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Figure 105 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
It is noted the original version of Fig. 105 (see Fig. 105 originally filed with PCT/US2022/022151, and Fig. 34 filed with the provisional application 63/167,462) was apparently taken from an internet site that is no longer accessible (noting the “Image source:…” caption with a URL in the original figures). An identical image, even using the same colors/shading, was published by Hoffman et al. (see Fig. 2 on p. 380). The three layer stack generically showing the BSI sensor, memory, and logic layers appears to be from derived Sony (see Feb. 2017 Sony News Release1 and Yokoyama et al. US 2019/0363129, Figs. 18-19) also showing the same three layer stack of a backside image sensor, a memory layer, and a logic circuit layer.
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Figure 105 filed with the PCT application.
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Figure 34 filed with provisional application.
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Figure 2 from Hoffman et al.
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Figures from Sony’s 2017 press release generically showing the same three layer stack.
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Figures 18-19 from Yokoyama et al. US 2019/0363129 (Sony)2.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 12-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 12 recites “one or more two-dimensional (2D)-die…comprise a light sensitive pixel array”, “a superstrate attached to one or more 2D-die”, “a fluid deployed between said one or more 2D-die and said product substrate”, and “a vector position of points on said one or more 2D-die and a vector position of corresponding points on said product substrate”, all lacking written description support. While it is acknowledged at the time of filing Applicant added ¶7 parroting claim 12, however the there is no written description support for one or more two-dimensional (2D)-die… comprise a light sensitive pixel array. As best understood, the light sensitive pixel array corresponds to the image sensor shown in Fig. 105, however there is no written description support with respect to the image sensor being a 2D-die. In fact, there is no detailed disclosure of any 2D-dies anywhere in the specification. Two dimensional (2D) materials in semiconductor devices are understood to be graphene, hexagonal boron nitride, molybdenum disulfide, and related materials consisting of a crystalline single layer of atoms. All known semiconductor dies are understood to be real/physical three dimensional (3D) objects having dimensions in x, y, and z directions. There are no details of 2D dies, how one produces, places or bonds a 2D die, or how a light sensitive pixel array (imager) is implemented in a 2D die. For the purpose of examination, a conventional semiconductor die will be treated as a “2D-die”. Next, the claim recites “a superstrate attached to one or more 2D-die”, having no written description support. Specifically with respect to the corresponding embodiment of the image sensor, there is no superstrate disclosed or shown in Fig. 105. The term superstrate only appears in claim 12 and corresponding ¶7 parroting claim 12. Next, the claim recites “a fluid deployed between said one or more 2D-die and said product substrate”, having no written description support. There is no disclosure of a fluid deployed between said one or more 2D-die and said product substrate, meaning the 2D-die and product substrate must be positioned such that the fluid is deployed, i.e. moved into place, delivered, or injected, etc., between the 2D-dies and the product substrate. This requires an undisclosed sequence. There is no written description support for deploying a fluid as claimed. There is no disclosure of how the claimed fluid enables precision overlay, or enables anything at all. Next, the claim recites “said precision overlay comprises a difference between a vector position of points on said one or more 2D-die and a vector position of corresponding points on said product substrate”. The vector position and points have no written description support. Aside from the claim text repeated in ¶7, the term vector does not appear in the original specification nor is there any description of any points or position thereof with respect to 2D-die or product substrate or how this relates to vector positions.
Claim 16 recites said 3D IC comprises a system designed using any of the following design approaches: a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation, a 3D logic implementation with a 2D memory implementation, and a 3D logic implementation with a 3D memory implementation, however none of these “design approaches” have written description support. There is no disclosure of any 2D logic, 3D logic, 2D memory, or 3D memory implementations, or any combinations thereof. According to claim 12, as best understood, the “one or more 2D-die comprise a light sensitive pixel array” is drawn to the 3D stacked image sensor shown in Fig. 105, however there is no disclosure of a “design approach” or any particular combination of a 2D or 3D logic implementation in conjunction with a 2D or 3D memory implementation.
Claim 20 recites a thickness of said one or more 2D-die is less than one of the following: 10 µm, 1 µm and 100 nm. There is no disclosure of a 2D die having a thickness in any of the claimed ranges nor is there any disclosure of picking, placing, and bonding dies having thicknesses in these ranges.
Claims 12-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 12-25 are product-by-process claims. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985).
In claim 12, as best understood, the claimed product is one or more 2D die comprising a light sensitive pixel array bonded to a product substrate. However, it is unclear if the claimed fluid is supposed to be present in the resulting product and if the resulting product is supposed to have structurally identifiable points on the die and/or product substrate. As best understood, the only figure showing the claimed light sensitive pixel array is Fig. 105 which appears to show three stacked dies/layers. As best understood, the figure shows no product substrate, no identifiable points on any die or product substrate, and no fluid making it unclear what Applicant regards as their claimed invention. Clam 12 recites “precision overlay”, rendering the claim indefinite since the claimed “precision” is a subjective term of degree, not defined in the claims or specification. It is not clear what Applicant regards as “precision” or to what degree of “precision” is required or how the term “precision” is intended to be interpreted. The term “precision” may refer to the ability of a measurement or calculation to be consistently reproduced or to the accuracy and exactness of a quality or condition. Next, the claims recite “precision overlay is enabled by a fluid deployed between said one or more 2D-die and said product substrate”. It is not clear how a fluid deployed between said die and product substrate enables precision overlay since there is no disclosure of a fluid deployed between said die and said product substrate. Next, it is unclear how precision overlay comprises a difference between a vector position of points on said die and a vector position of corresponding points on said product substrate since there is no disclosure of any vector positions of any points on any dies or product substrates, differences thereof, or any reference or origin disclosed. It is unclear how to interpret a vector position of points on four or more die or the corresponding points on a product substrate. Points on four or more dies are simply points somewhere on dies, a vector is not simply a combination of points, a vector is a quantity having a magnitude and direction, and a position vector would require a position at least with respect to some unknown origin or reference point and each point on each die and substrate. Furthermore, the recited a vector position [singular] of points [plural] on die(s) or on a product substrate does not make sense. The specification provides no guidance with respect to the claimed vector position or points or how these are determined. It is unclear how to interpret these limitations in the claims.
Claim 13 recites said 3D IC is an application specific integrated circuit (ASIC) system, rendering the claim indefinite. Since there is no application specific integrated circuit (ASIC) system disclosed, it is unclear what is required or excluded by the claimed application specific integrated circuit (ASIC) system. It is not clear what Applicant regards as an ASIC. For the purpose of examination, an image sensor die is considered an ASIC. Also, since claim 13 must further limit claim 12 which already introduces a die comprising a light sensitive pixel array, understood to correspond to the image sensor in Fig. 105, an image sensor being an ASIC, it is unclear what additional structure or function is provided by referring to the 3D IC, already comprising an ASIC, as an ASIC system or if this designation somehow further introduces structure or function.
Claim 14 recites said 3D IC is a system-on-a-chip (SoC), rendering the claim indefinite. Since there is no a system-on-a-chip (SoC) disclosed, it is unclear what is required or excluded by the claimed a system-on-a-chip (SoC). Does Applicant consider a die comprising a light sensitive pixel array bonded to a product substrate a SoC? It is unclear what additional structure of function is provided by referring to the 3D IC as a SoC, nor is it clear when one or more dies comprising a light sensitive pixel array bonded to a product substrate become a SoC or what additional features or structure is necessary for the 3D IC to be a SoC. A system on a chip (SoC) is generally understood to be an integrated circuit that combines most or all key components of a computer or electronic system onto a single microchip, however the 3D IC described appears to be one or more dies bonded to a product substrate wherein at lest one die is an image sensor die and the other dies are logic and memory dies (Fig. 105, also noting claim 15), none of which are understood to be a SoC based on the conventional use of the term since the individual functions (memory, logic, and image sensor) are individually performed by a different die rather than a single die. For the purpose of examination, a bonded stack of dies comprising an image sensor, memory, and logic circuitry will be broadly treated as a SoC.
Claim 16 recites said 3D IC comprises a system designed using any of the following design approaches: a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation, a 3D logic implementation with a 2D memory implementation, and a 3D logic implementation with a 3D memory implementation. Claim 16 is indefinite because it is unclear what resulting structure or function is required or excluded by reciting “…a system designed using any of the following design approaches…” or how any of the claimed design approaches result in a particular structure or function, nor is it clear what applicant regards as 2D or 3D logic or memory implementations as there are no design approaches or 2D or 3D logic or memory implementations disclosed making it unclear when infringement occurs. It is also not clear if something designed using a design approach such as “a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation” means the actual device includes a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation or if these undefined implementations are simply used in the design.
Claim 17 recites said 3D IC comprises a system that utilizes one or more of the following: Static Random Access Memory (SRAM), 3D SRAM, 3D stand-alone stacked SRAM, a 3D only-bitcell stacked SRAM, Dynamic Random Access Memory (DRAM), 3D DRAM, analog IP and input/output. It is not clear what is required or excluded by reciting a system that utilizes… various memory and/or “analog IP and input/output”. No 3D IC systems utilizing any of the following memory or “analog IP and input/output” are disclosed, it is unclear what system of the 3D IC utilizes any of the claimed memory or analog IP and input/output or how these features must relate or correspond to one another. It is not clear if the 3D IC physically includes these features in the device structure or if the system utilizing these features uses features located elsewhere, i.e. an IC can be connected to a computer that is connected to the internet and running a search query could access and utilize memory on another computer located elsewhere in the world. Also, since there is no disclosure of the claimed 3D SRAM, 3D stand-alone stacked SRAM, a 3D only-bitcell stacked SRAM, 3D DRAM, or analog IP and input/output, it is not clear what Applicant regards as these features or when a system utilizes one or more of the claimed features.
Claim 18 recites said one or more 2D-die comprise multiple die. Claim 12 recites “one or more 2D die” several times. It is unclear what is required in claim 12 if the “one or more 2D-die” now comprises multiple die since the “one or more 2D-die” in line 2 of claim 12 may now refer to a plurality of die while the subsequent limitations still recite “one or more 2D-die” and can still be met by the “one” option recited thereby not requiring the “or more”. It is unclear what is actually required with respect to the resulting product in view of the one or more 2D-die comprise multiple die.
Claim 19 recites said precision overlay between said one or more 2D-die and said product substrate is achieved using a nanometer overlay metrology scheme. Since there is no “nanometer overlay metrology scheme” expressly defined in the specification or claims, the metes and bounds are unclear. There is no standardized nanometer overlay metrology scheme, the specification does not define this scheme, one would not know what is required or excluded in such a scheme, therefore one would be unable to determine when infringement occurs.
Claim 20 recites a thickness of said one or more 2D-die is less than one of the following: 10 µm, 1 µm and 100 nm. The recited “less than” renders the claim indefinite as there are no lower limits. All dies must have a non-zero thickness. The claimed ranges include a 1 nm thick or a 1 Å thick die. A die having a thickness in the claimed range, e.g. a 1 nm thick or a 1 Å thick die, would have no mechanical integrity. Applicant does not disclose any dies having thicknesses in the claimed ranges or how to pick, place, and bond dies having thicknesses in the claimed ranges.
Claim 24 recites wherein said 3D IC is an imager. It is not clear what additional structure or function is required or excluded by reciting the 3D IC is an imager when according to claim 12, the 3D IC already comprises “a light sensitive pixel array”. The claimed “light sensitive pixel array” is understood to be the imager shown in Fig. 105.
Claim 25 recites said imager is curved, however no figures show a curved imager making it unclear what Applicant regards as a curved imager or what parts of the imager are supposed to be curved and to what degree.
Claims 13, 14, 19, 21, 22, 23, and 24 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 13 recites said 3D IC is an application specific integrated circuit (ASIC) system. As best understood, the light sensitive pixel array recited in claim 12 can be construed as an ASIC, therefore claim 13 provides no additional structure or function to the 3D IC already recited in claim 12 and does not further limit claim 12.
Claim 14 recites said 3D IC is a system-on-a-chip (SoC). Claim 14 simply stating the 3D IC is a SoC provides no additional structure or function to the 3D IC already recited in claim 12 and does not further limit claim 12.
Claim 19 recites said precision overlay between said one or more 2D-die and said product substrate is achieved using a nanometer overlay metrology scheme. Claim 19 adds no additional structure or function and therefore does not further limit the 3D IC of claim 12.
Claim 21 recites said source wafer is one of the following: a silicon wafer, a non-silicon wafer comprising GaN, GaAs, InP or SiC, and sapphire. The source wafer is not part of the resulting product, thus the material of the source wafer does not further limit the 3D IC of claim 12.
Claim 22 recites said source wafer incorporates a sacrificial layer. The source wafer with a sacrificial layer is not part of the resulting product and a sacrificial layer of the source wafer does not further limit the 3D IC of claim 12.
Claim 23 recites said source wafer incorporated with said sacrificial layer is constructed from a substrate with two or more layers of differing doping levels and/or types. The source wafer constructed from a substrate with two or more layers of differing doping levels and/or types is not part of the resulting product and a substrate with two or more layers of differing doping levels and/or types of the source wafer does not further limit the 3D IC of claim 12.
Claim 24 recites said 3D IC is an imager, however claim 12 already recites said one or more 2D-die comprise “a light sensitive pixel array”, understood to be the imager shown in Fig. 105, therefore claim 24 provides no additional structure or function to the 3D IC already recited in claim 12 and does not further limit claim 12.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-19 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Yokoyama et al. (US 2019/0363129).
(Re Claim 12) A three-dimensional (3D) integrated circuit (IC), comprising:
one or more two-dimensional (2D)-die, wherein said one or more 2D-die are fabricated by assembling said one or more 2D-die onto a product substrate, wherein one or more of said one or more 2D-die comprise a light sensitive pixel array, wherein said assembling is enabled by:
selectively picking said one or more 2D-die from a source wafer by a superstrate attached to said one or more 2D-die; and
placing and bonding said selectively picked one or more 2D-die onto said product substrate with precision overlay, wherein said precision overlay is enabled by a fluid deployed between said one or more 2D-die and said product substrate, wherein said precision overlay comprises a difference between a vector position of points on said one or more 2D-die and a vector position of corresponding points on said product substrate.
Claim 12 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985).
In this case, as best understood (also see §112 rejections above), the claimed 3D IC product comprises one or more two-dimensional (2D)-die, wherein one or more 2D-die comprise a light sensitive pixel array, and wherein one or more 2D-die are bonded to a product substrate. The resulting 3D IC product need not be formed by the recited assembling process. The resulting 3D IC structure is the same regardless of the process of assembling employing a source substrate, a superstrate, picking and placing, a fluid deployed between one or more 2D-die and product substrate, and/or a vector position of points corresponding to the die(s) and product substrate.
Yokoyama teaches a bonded stack of dies including an imager die (300), the lowermost die can be construed as a product substrate (see Figs. 18-19). This anticipates the claimed 3D IC structure. This appears to be the same structure depicted by Applicant (Fig. 105). Regarding the obviousness, it is obvious the structure shown in Figs. 18-19 is the same resulting structure regardless of where the dies previously came from or whatever processes were used to pick, place, and bond the 3D IC.
Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
(Re Claim 13) wherein said 3D IC is an application specific integrated circuit (ASIC) system (Figs. 18-19, an image sensor is understood to be an ASIC).
(Re Claim 14) wherein said 3D IC is a system-on-a chip (SoC) (Figs. 18-19, the combination of the imager, memory, and logic is understood to be a SoC).
(Re Claim 15) wherein said 3D IC comprises logic and memory circuitry (Figs. 18-19, memory in 100, logic in 200).
(Re Claim 16) wherein said 3D IC comprises a system designed using any of the following design approaches: a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation, a 3D logic implementation with a 2D memory implementation, and a 3D logic implementation with a 3D memory implementation (Figs. 18-19, the system was apparently designed using a real/physical 3D memory chip and real/physical 3D logic chip).
(Re Claim 17) wherein said 3D IC comprises a system that utilizes one or more of the following: Static Random Access Memory (SRAM), 3D SRAM, 3D stand-alone stacked SRAM, a 3D only-bitcell stacked SRAM, Dynamic Random Access Memory (DRAM), 3D DRAM, analog IP and input/output (the system comprises DRAM and apparently I/O, ¶¶63, 116).
(Re Claim 18) wherein said one or more 2D-die comprise multiple die (Figs. 18-19 depicting multiple bonded stacked die).
(Re Claim 19) wherein said precision overlay between said one or more 2D-die and said product substrate is achieved using a nanometer overlay metrology scheme (Figs. 18-19, showing the dies are assembled using precision overlay, however this claim relates to process limitations of these product-by-process claims and is not physically part of or present in the resulting product, also see §112 rejections above).
(Re Claims 21-23) wherein said source wafer is one of the following: a silicon wafer, a non-silicon wafer comprising GaN, GaAs, InP or SiC, and sapphire;
wherein said source wafer incorporates a sacrificial layer; and
wherein said source wafer incorporated with said sacrificial layer is constructed from a substrate with two or more layers of differing doping levels and/or types.
The source wafer claimed relates to the process limitations in these product-by-process claims. The source wafer, sacrificial layer thereof, and any doped layers thereof are not present in the resulting 3D IC product. Limitations regarding the source wafer are inconsequential with respect to the 3D IC product claimed. Also see §112 rejections above.
(Re Claim 24) wherein said 3D IC is an imager (Figs. 18-19, the device is an imager).
(Re Claim 25) wherein said imager is curved (Figs. 18-19, the imager is curved at microlens 33).
Claim 20 is rejected under 35 U.S.C. 103 as obvious over Yokoyama et al. (US 2019/0363129) in view of Yoshihara et al. (US 2012/0056288).
(Re Claim 20) wherein a thickness of said one or more 2D-die is less than one of the following: 10 µm, 1 µm and 100 nm.
Yokoyama is silent regarding the thickness of the dies. A PHOSITA desiring to make and use Yokoyama’s 3D IC would be motivated to look to related art to teach suitable thicknesses for the dies. Related art from Yoshihara teaches thicknesses for the chips are in the range of less than 10 µm (¶¶119, 221, 326, 364). In light of Yoshihara, a PHOSITA would find it obvious to use thin dies having a thickness of less than 10 µm. The advantage of using thin dies in an image sensor stack is enabling compact, high-performance designs, specifically by facilitating backside illumination for superior light sensitivity and signal-to-noise ratio, and allowing for 3D stacking to integrate more processing power and functionality within a smaller form factor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches pertinent image sensor dies bonded to other dies and/or various substrates.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
1 Accessible at Internet Archive, archive copy from Feb. 9, 2017: https://web.archive.org/web/20170209155054/http://www.sony.net/SonyInfo/News/Press/201702/17-013E/index.html
2 Additional related art is cited on the PTO-892.