DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/29/2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I and Claims 1-18 in the reply filed on 04/10/2026 is acknowledged. Claims 19-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/10/2026.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 recites “wherein the organic dielectric comprises a first thickness”; this should be written as “wherein the organic dielectric material comprises a first thickness”
Claim 17 recites “wherein the organic dielectric comprises a first thickness”; this should be written as “wherein the organic dielectric material comprises a first thickness”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "dielectric material" in line 1. There is insufficient antecedent basis for this limitation in the claim.
The term “elsewhere” in claims 8 and 17 is a relative term which renders the claim indefinite. The term “elsewhere” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation “second thickness” is rendered indefinite by use of the term “elsewhere”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9-14, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20220375839A1; hereinafter Chen) in view of Sun et al. (US20230369261A1; hereinafter Sun).
Regarding Claim 1, Chen discloses an apparatus (semiconductor package, [0011]) comprising:
a plurality of interconnect layers (Redistribution lines RDL 26, 32) within a substrate (interposer 100, [0034]), FIG. 2, [0017].
a layer of organic dielectric material (dielectric layer 34 formed of polymer) over the plurality of interconnect layers (26, 32), FIG. 3, [0018].
copper pads (66) within the layer of inorganic dielectric material (64),FIG. 11, [0033];
a first integrated circuit device (device die 68A) copper-to-copper bonded with the copper pads (device die 68A includes bond pads 74A which is bonded to bond pads 66 through copper-to-copper direct bonding), FIG. 12, [0036], [0037];
inorganic dielectric material (gap-filling material 80 formed of silicon oxide) over the layer of organic dielectric material (34), the inorganic dielectric material (80) embedding the first integrated circuit device (68A), and the inorganic dielectric material extending across a width of the substrate (80 is deposited and planarized extending across the substrate 100), FIG. 14, [0040]; and
a second integrated circuit device (168A) coupled with a substrate surface (bond pads 174A of 168A coupled to the upper surface of substrate 70A via TSVs 71A and TDVs 162) above the inorganic dielectric material (80), FIG. 21 reproduced below, [0045].
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Chen: FIG. 21
Chen does not disclose “copper pads within the layer of organic dielectric material.”
In a similar art, Sun discloses packages with substrates and integrated devices [0003].
Sun discloses: copper pads (interconnects 1214 including via, pad, and/or traces) within the layer of organic dielectric material (1222 made of polyimide, [0119]), FIG. 12B, [0121].
Sun [0126], [0127] discloses the seed layer 1201 may include copper and the metal layers are patterned to form interconnects by plating, indicating the interconnect 1214 including the pads may be made of copper.
Sun discloses the integrated device 105 is coupled with the top surface of 104 via interconnects 150 and 142, above the encapsulation layer 106, FIG. 1 reproduced below, [0026], [0032].
The combination of Chen and Sun discloses: a second integrated circuit device coupled with a substrate surface (Sun: integrated device 105 coupled with the top surface of 104 via interconnects 150 and 142, FIG. 1, [0032]) above the inorganic dielectric material (Chen: gap-filling material 80 formed of oxide, [0040]).
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Sun: FIG. 1
Sun discloses that a device as taught facilitates electrical connection and improves package performance [0138]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s device in order to facilitate electrical connection and improve package performance as disclosed by Sun [0138].
Regarding Claim 2, The combination of Chen and Sun discloses the apparatus of claim 1.
Chen discloses: wherein the layer of organic dielectric material (34 may be formed of PBO, polyimide, BCB, or the like, [0018]) comprises a photo imageable dielectric (photo-sensitive materials are polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, [0014]).
Regarding Claim 3, The combination of Chen and Sun discloses the apparatus of claim 2.
Chen discloses: wherein the layer of organic dielectric material (34) comprises a polyimide [0018].
Regarding Claim 4, The combination of Chen and Sun discloses the apparatus of claim 1.
Chen does not disclose “wherein the first integrated circuit device comprises a bridge device that communicatively couples the second integrated circuit device with a third integrated circuit device.”
Sun discloses: wherein the first integrated circuit device comprises a bridge device (interconnection die 101) that communicatively couples the second integrated circuit device (105) with a third integrated circuit device (103), FIG. 1, [0032].
Sun discloses that a device as taught facilitates electrical connection and improves package performance [0138]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s device in order to facilitate electrical connection and improve package performance as disclosed by Sun [0138].
Regarding Claim 5, The combination of Chen and Sun discloses the apparatus of claim 4.
Chen discloses: wherein the second integrated circuit device comprises a processor (168A includes a logic die which may be an application processor die, [0035], [0043]) and the third integrated circuit device comprises a memory device (212 may be a memory stack, [0057]).
Regarding Claim 7, The combination of Chen and Sun discloses the apparatus of claim 1.
Chen discloses: further comprising a plurality of copper pillars (TDVs 162 formed of copper [0032]) within the inorganic dielectric material (80), the plurality of copper pillars coupled with the plurality of interconnect layers (RDL 26, 32), FIG. 17, [0041].
Regarding Claim 9, The combination of Chen and Sun discloses the apparatus of claim 1.
Chen discloses: wherein the first integrated circuit device (68A) comprises a device chosen from the group consisting of: high bandwidth memory (HBM), intelligent power device (IPD), photonic integrated circuit (PIC), and embedded passive components (EPC), [0035], [0057].
Chen [0035] discloses the device die 68A may include a memory die, and [0057] discloses bonding a HBM 212 onto the package structure, it would be obvious to implement the device die 68A as a high bandwidth memory (HBM) to improve performance.
Regarding Claim 10, The combination of Chen and Sun discloses the apparatus of claim 1.
Chen discloses: wherein the dielectric material (80) comprises silicon oxide, [0046].
Regarding Claim 11, Chen discloses a system (package [0038]) comprising:
a host board (Printed Circuit Board (PCB) that will be bonded to interposer substrate 100), [0038];
an integrated circuit device package (package 104), FIG. 28A, [0059], the integrated circuit device package comprising:
a plurality of interconnect layers (Redistribution lines RDL 26, 32) within a substrate (interposer 100, [0034]), FIG. 2, [0017].
a layer of organic dielectric material (dielectric layer 34 formed of polymer) over the plurality of interconnect layers (26, 32), FIG. 3, [0018].
copper pads (66) within the layer of inorganic dielectric material (64),FIG. 11, [0033];
a first integrated circuit device (device die 68A) copper-to-copper bonded with the copper pads (device die 68A includes bond pads 74A which is bonded to bond pads 66 through copper-to-copper direct bonding), FIG. 12, [0036], [0037];
dielectric material (gap-filling material 80 formed of oxide) over the layer of organic dielectric material (34), the dielectric material (80) embedding the first integrated circuit device (68A), and the dielectric material extending across a width of the substrate (80 is deposited and planarized extending across the substrate 100), FIG. 14, [0040]; and
a second integrated circuit device (168A) coupled with a substrate surface (bond pads 174A of 168A coupled to the upper surface of substrate 70A via TSVs 71A and TDVs 162) above the inorganic dielectric material (80), FIG. 21, [0045].
a power supply to provide power to the integrated circuit device package (104) through the host board (PCB), FIG. 28A, [0059].
Chen [0059] discloses formation of electrical connectors 110 which may be metal bumps, solder bumps, metal pillars, wire bonds, or other applicable connectors. Chen [0038] discloses a PCB bonded to interposer substrate 100 of the package 104. Thus connectors 110 electrically couple the package to the PCB, enabling power from a power supply to be delivered to the integrated circuit package through the PCB.
Chen does not disclose “copper pads within the layer of organic dielectric material.”
In a similar art, Sun discloses packages with substrates and integrated devices. [0003].
Sun discloses: copper pads (interconnects 1214 including via, pad, and/or traces) within the layer of organic dielectric material (1222 made of polyimide, [0119]), FIG. 12B, [0121].
Sun [0126], [0127] discloses the seed layer 1201 may include copper and the metal layers are patterned to form interconnects by plating, indicating the interconnect 1214 including the pads may be made of copper.
Sun discloses the integrated device 105 is coupled with the top surface of 104 via interconnects 150 and 142, above the encapsulation layer 106, FIG. 1, [0026], [0032].
The combination of Chen and Sun discloses: a second integrated circuit device coupled with a substrate surface (Sun: integrated device 105 coupled with the top surface of 104 via interconnects 150 and 142, FIG. 1, [0032]) above the inorganic dielectric material (Chen: gap-filling material 80 formed of oxide, [0040]).
Sun discloses that a device as taught facilitates electrical connection and improves package performance [0138]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s device in order to facilitate electrical connection and improve package performance as disclosed by Sun [0138].
Regarding Claim 12, The combination of Chen and Sun discloses the system of claim 11.
Chen discloses: wherein the layer of organic dielectric material (34 may be formed of PBO, polyimide, BCB, or the like, [0018]) comprises a photo imageable dielectric (photo-sensitive materials are polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, [0014]).
Regarding Claim 13, The combination of Chen and Sun discloses the system of claim 11.
Chen does not disclose “wherein the first integrated circuit device comprises a bridge device that communicatively couples the second integrated circuit device with a third integrated circuit device.”
Sun discloses: wherein the first integrated circuit device comprises a bridge device (interconnection die 101) that communicatively couples the second integrated circuit device (105) with a third integrated circuit device (103), FIG. 1, [0032].
Sun discloses that a device as taught facilitates electrical connection and improves package performance [0138]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s device in order to facilitate electrical connection and improve package performance as disclosed by Sun [0138].
Regarding Claim 14, The combination of Chen and Sun discloses the system of claim 13.
Chen discloses: wherein the second integrated circuit device comprises a processor (168A includes a logic die which may be an application processor die, [0035], [0043]) and the third integrated circuit device comprises a memory device (212 may be a memory stack, [0057]).
Regarding Claim 16, The combination of Chen and Sun discloses the system of claim 11.
Chen discloses: further comprising a plurality of copper pillars (TDVs 162 formed of copper [0032]) within the dielectric material (80), the plurality of copper pillars coupled with the plurality of interconnect layers (RDL 26, 32), FIG. 17, [0041].
Regarding Claim 18, The combination of Chen and Sun discloses the system of claim 11.
Chen discloses: wherein the dielectric material (80) comprises silicon oxide, [0046].
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sun, further in view of Ma et al. (US20160284637A1; hereinafter Ma).
Regarding Claim 6, The combination of Chen and Sun discloses the apparatus of claim 1.
Chen does not disclose “further comprising a glass core coupled with the plurality of interconnect layers.” Sun discloses in aspect 6, the package includes a glass die substrate [0140].
In a similar art, Ma discloses substrates for integrated circuit devices [0002].
Ma discloses: further comprising a glass core (a substrate 100 having a core 150 comprised of a glass, [0033]) coupled with the plurality of interconnect layers (metal layers 136a/146a), FIG. 1B, 1C, [0043].
Ma [0043] discloses the conductors 160 extend through the glass core 150 and electrically couples metal layers 136a/146a through vias 139a/149a in build-up structures 130/140.
Ma discloses that a device as taught enables the implementation of higher I/O packages and improves reliability [0092]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sun’s device in order to improve electrical insulation and increase reliability as disclosed by Ma [0092].
Regarding Claim 15, The combination of Chen and Sun discloses the system of claim 11.
Chen does not disclose “further comprising a glass core coupled with the plurality of interconnect layers.” Sun discloses in aspect 6, the package includes a glass die substrate [0140].
Ma discloses: further comprising a glass core (a substrate 100 having a core 150 comprised of a glass, [0033]) coupled with the plurality of interconnect layers (metal layers 136a/146a), FIG. 1B, 1C, [0043].
Ma [0043] discloses the conductors 160 extend through the glass core 150 and electrically couples metal layers 136a/146a through vias 139a/149a in build-up structures 130/140.
Ma discloses that a device as taught enables the implementation of higher I/O packages and improves reliability [0092]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sun’s device in order to improve electrical insulation and increase reliability as disclosed by Ma [0092].
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sun, further in view of Raorane et al. (US20190341342A1; hereinafter Raorane).
Regarding Claim 8, The combination of Chen and Sun discloses the apparatus of claim 1.
The combination of Chen and Sun does not disclose “wherein the organic dielectric comprises a first thickness below the first integrated circuit device and a second thickness elsewhere, the first thickness being greater than the second thickness.”
In a similar art, Raorane discloses semiconductor packages and methods of forming such semiconductor packages [0013].
Raorane discloses: wherein the organic dielectric (110) comprises a first thickness (thickness T11) below the first integrated circuit device (414, FIG. 4, [0074]) and a second thickness (thickness T12) elsewhere, the first thickness being greater than the second thickness (the first dielectric thickness T11 may be greater than the second dielectric thickness T12 within the first dielectric 110), FIG. 1, [0030].
Raorane [0074] discloses implementing a first dielectric having a first thickness that varies from a second thickness of a first/second dielectric based on optimizing each IC of the build-up structure to have improved electrical performances; [0030] discloses the first dielectric thickness T11 may be greater than the second dielectric thickness T12 within the first dielectric 110, indicating the dielectric may have first thickness provided below the first integrated circuit device and a second thickness elsewhere with the first thickness greater than the second thickness.
Raorane discloses that a device as taught improves electrical performance of the device [0074]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sun’s device in order to improve electrical performance as disclosed by Raorane [0074].
Regarding Claim 17, The combination of Chen and Sun discloses the system of claim 11.
The combination of Chen and Sun does not disclose “wherein the organic dielectric comprises a first thickness below the first integrated circuit device and a second thickness elsewhere, the first thickness being greater than the second thickness.”
Raorane discloses: wherein the organic dielectric (110) comprises a first thickness (thickness T11) below the first integrated circuit device (414, FIG. 4, [0074]) and a second thickness (thickness T12) elsewhere, the first thickness being greater than the second thickness (the first dielectric thickness T11 may be greater than the second dielectric thickness T12 within the first dielectric 110), FIG. 1, [0030].
Raorane [0074] discloses implementing a first dielectric having a first thickness that varies from a second thickness of a first/second dielectric based on optimizing each IC of the build-up structure to have improved electrical performances; [0030] discloses the first dielectric thickness T11 may be greater than the second dielectric thickness T12 within the first dielectric 110, indicating the dielectric may have first thickness provided below the first integrated circuit device and a second thickness elsewhere with the first thickness greater than the second thickness.
Raorane discloses that a device as taught improves electrical performance of the device [0074]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Sun’s device in order to improve electrical performance as disclosed by Raorane [0074].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna J Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST.
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/Krishna J. Palaniswamy/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899