Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the cylindrical shape from plan view in claims 2 and 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 2 and 7, both claims recite the limitation regarding the shape of the capacitors as having a “cylindrical shape from the plan view perspective.” As a cylinder is a 3D object and a plan view refers to a top down view typically represented in 2D, it is not immediately clear to a person of ordinary skill in the art which shapes a cylindrical shape in plan view would entail. Additionally, combined with the fact that the claimed subject matter is not within the drawings, see above drawings objection, the claims fail to particularly point out and distinctly claim the subject matter. In the interest of compact prosecution, examiner will interpret the claim to mean that the capacitors are shaped like a cylinder, or that they have a circular shape from plan view.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20100112753A1) in view of Kajiyama (US20120008367A1).
Regarding claim 1, Lee discloses an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (See below annotated fig. 2 capacitor array defined by capacitor electrodes 132/134 coupled to plurality of bit lines 172);
a memory transistor layer beneath the memory structure layer (See below annotated fig. 2 transistor layer defined by semiconductor layers 206/204/202. Examiner notes par. 25 of the application which states “terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made” and so Lee’s fig. 2 will be referred to upside down as shown below by annotated fig. 2 in order to be consistent with applicant’s definitions), the memory transistor layer coupled to corresponding capacitors of the capacitor array of the memory structure layer (See below annotated fig. 2 the memory transistor layer is coupled to corresponding above capacitors); and
a select transistor layer over the memory structure layer (See below annotated fig. 2 select transistor layer above first memory structure), the select transistor layer including backend transistors having a channel composition different than the front end transistors (Par. 42 “[t]he semiconductor substrate 100 can include bulk silicon, bulk silicon-germanium, or semiconductor substrate with silicon or silicon-germanium epitaxial layer” while par. 52 teaches that “the semiconductor layer patterns 202, 204, 206 can be formed with…single crystalline semiconductor” materials and so the select transistor layer channel can include SiGe while the backend transistor channel structure can comprise single crystalline Si), wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (See below annotated fig. 2A semiconductor layer patterns 202/204/206 coupled to bit lines 172).
Lee does not appear to teach
the memory transistor layer including front end fin-based transistors.
Kajiyama teaches
the memory transistor layer including front end fin-based transistors (Par. 140 “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Kajiyama because “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics” (Kajiyama par. 140).
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Regarding claim 2, the combination of Lee and Kajiyama teaches the integrated circuit structure of claim 1,
wherein each capacitor of the capacitor array of the memory structure layer has a cylindrical shape from the plan view perspective (Lee par. 46 “the capacitors can be formed as cylindrical structure or stacked structure”).
Regarding claim 3, the combination of Lee and Kajiyama teaches the integrated circuit structure of claim 1,
wherein the front end fin-based transistors are single crystalline silicon fin-based transistors (Lee teaches the use of a single crystalline silicon based transistor and Kojima teaches the use of a finFET so the combination of Lee and Kajiyama teaches wherein the front end fin-based transistors are single crystalline silicon fin-based transistors, see above rejection of claim 1).
Regarding claim 4, the combination of Lee and Kajiyama teaches the integrated circuit structure of claim 1, further comprising:
a second memory structure layer beneath the memory transistor layer, the second memory structure layer including a second capacitor array coupled to a second plurality of plate lines (See above annotated fig. 2 second capacitor array defined by capacitor electrodes 284/282 coupled to a plurality of bit lines 252).
Regarding claim 5, the combination of Lee and Kajiyama teaches the integrated circuit structure of claim 4,
wherein one or more backend transistors of the select transistor layer is coupled to the second plurality of plate lines of the second memory structure layer (Lee fig. 2 logic transistors 110/112 coupled to bit lines 252 through wirings 164).
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20100112753A1) in view of Li et al. (US20130270508A1, hereinafter Li).
Regarding claim 6, Lee teaches an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (See above annotated fig. 2 capacitor array defined by capacitor electrodes 132/134 coupled to plurality of bit lines 172);
a memory transistor layer beneath the memory structure layer (See above annotated fig. 2 transistor layer defined by semiconductor layers 206/204/202. Examiner notes par. 25 of the application which states “terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made” and so Lee’s fig. 2 will be referred to upside down as shown below by annotated fig. 2 in order to be consistent with applicant’s definitions), the memory transistor layer transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer (See above annotated fig. 2 the memory transistor layer is coupled to corresponding above capacitors); and
a select transistor layer over the memory structure layer (See above annotated fig. 2 select transistor layer above first memory structure), the select transistor layer including backend transistors having a channel composition different than the front end transistors (Par. 42 “[t]he semiconductor substrate 100 can include bulk silicon, bulk silicon-germanium, or semiconductor substrate with silicon or silicon-germanium epitaxial layer” while par. 52 teaches that “the semiconductor layer patterns 202, 204, 206 can be formed with…single crystalline semiconductor” materials and so the select transistor layer channel can include SiGe while the backend transistor channel structure can comprise single crystalline Si), wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (See above annotated fig. 2A semiconductor layer patterns 202/204/206 coupled to bit lines 172).
Lee does not appear to teach
the memory transistor layer including front end nanowire-based transistors.
Li teaches
the memory transistor layer including front end nanowire-based transistors (Par. 46 “[a] standard vertical nanowire transistor process may be used to form the select transistor for the memory cell and array”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Li as both Lee and Li teach suitable types of transistor for use as select transistor in a memory array, it would have been obvious to substitute Lee’s select transistors with Li’s nanowire-based select transistors to achieve the predictable result of forming nanowire-based select transistors.
Regarding claim 7, the combination of Lee and Li teaches the integrated circuit structure of claim 6,
wherein each capacitor of the capacitor array of the memory structure layer has a cylindrical shape from the plan view perspective (Lee par. 46 “the capacitors can be formed as cylindrical structure or stacked structure”).
Regarding claim 8, the combination of Lee and Li teaches the integrated circuit structure of claim 6,
wherein the front end nanowire-based transistors are single crystalline silicon nanowire-based transistors (Lee teaches the use of a single crystalline silicon based transistor and Kojima teaches the use of a finFET so the combination of Lee and Li teaches wherein the front end fin-based transistors are single crystalline silicon fin-based transistors, see above rejection of claim 1).
Regarding claim 9, the combination of Lee and Li teaches the integrated circuit structure of claim 6, further comprising:
a second memory structure layer beneath the memory transistor layer, the second memory structure layer including a second capacitor array coupled to a second plurality of plate lines (See above annotated fig. 2 second capacitor array defined by capacitor electrodes 284/282 coupled to a plurality of bit lines 252).
Regarding claim 10, the combination of Lee and Li teaches the integrated circuit structure of claim 9,
wherein one or more backend transistors of the select transistor layer is coupled to the second plurality of plate lines of the second memory structure layer (Lee fig. 2 logic transistors 110/112 coupled to bit lines 252 through wirings 164).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20100112753A1) in view of Kajiyama (US20120008367A1) and LaJoie et al. (US20200098932A1, hereinafter LaJoie).
Regarding claim 11, Lee teaches the component including an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (See above annotated fig. 2 capacitor array defined by capacitor electrodes 132/134 coupled to plurality of bit lines 172);
a memory transistor layer beneath the memory structure layer (See above annotated fig. 2 transistor layer defined by semiconductor layers 206/204/202. Examiner notes par. 25 of the application which states “terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made” and so Lee’s fig. 2 will be referred to upside down as shown below by annotated fig. 2 in order to be consistent with applicant’s definitions), the memory transistor layer coupled to corresponding capacitors of the capacitor array of the memory structure layer (See above annotated fig. 2 the memory transistor layer is coupled to corresponding above capacitors); and
a select transistor layer over the memory structure layer (See above annotated fig. 2 select transistor layer above first memory structure), the select transistor layer including backend transistors having a channel composition different than the front end transistors (Par. 42 “[t]he semiconductor substrate 100 can include bulk silicon, bulk silicon-germanium, or semiconductor substrate with silicon or silicon-germanium epitaxial layer” while par. 52 teaches that “the semiconductor layer patterns 202, 204, 206 can be formed with…single crystalline semiconductor” materials and so the select transistor layer channel can include SiGe while the backend transistor channel structure can comprise single crystalline Si), wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (See above annotated fig. 2A semiconductor layer patterns 202/204/206 coupled to bit lines 172).
Lee does not appear to teach
a computing device, comprising:
a board;
a component coupled to the board; and
the memory transistor layer including front end fin-based transistors.
Kajiyama teaches
the memory transistor layer including front end fin-based transistors (Par. 140 “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics”).LaJoie teaches
a board (Fig. 7 integrated circuit die 702); and
a component coupled to the board (Fig. 7 processor 704 coupled to integrated circuit die 702).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Kajiyama because “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics” (Kajiyama par. 140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Kajiyama with the teachings of LaJoie because LaJoie teaches the technique of integrating a memory device, such as the one taught by the combination of Lee and Kajiyama, into a larger computing device as represented by LaJoie’s fig. 7.
Regarding claim 12, the combination of Lee, Kajiyama, and LaJoie teaches the computing device of claim 11, further comprising:
a memory coupled to the board (LaJoie fig. 7 on-die memory 706 coupled to integrated circuit die 702. As LaJoie teaches the technique of integrating a device as taught by the combination of Lee and Kajiyama into a larger computing device, they also teach the other associated components in fig. 7 which includes a memory coupled to the board).
Regarding claim 13, the combination of Lee, Kajiyama, and LaJoie teaches the computing device of claim 11, further comprising:
a communication chip coupled to the board (LaJoie fig. 7 communications chip 708. As LaJoie teaches the technique of integrating a device as taught by the combination of Lee and Kajiyama into a larger computing device, they also teach the other associated components in fig. 7 which includes a communication chip coupled to the board).
Regarding claim 14, the combination of Lee, Kajiyama, and Lajoie teaches the computing device of claim 11,
wherein the component is a packaged integrated circuit die (LaJoie par. 83 “[t]he processor 704 of the computing device 700 includes one or more devices, such as transistors” and so the processor is a packaged integrated circuit die).
Regarding claim 15, the combination of Lee, Kajiyama, and Lajoie teaches the computing device of claim 11,
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (LaJoie fig. 7 processor 704 is a processor).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US20100112753A1) in view of Li (US20130270508A1) and LaJoie (US20200098932A1).
Regarding claim 16, Lee teaches the component including an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (See above annotated fig. 2 capacitor array defined by capacitor electrodes 132/134 coupled to plurality of bit lines 172);
a memory transistor layer beneath the memory structure layer (See above annotated fig. 2 transistor layer defined by semiconductor layers 206/204/202. Examiner notes par. 25 of the application which states “terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made” and so Lee’s fig. 2 will be referred to upside down as shown below by annotated fig. 2 in order to be consistent with applicant’s definitions), the memory transistor layer including front end nanowire-based transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer (See above annotated fig. 2 the memory transistor layer is coupled to corresponding above capacitors); and
a select transistor layer over the memory structure layer (See above annotated fig. 2 select transistor layer above first memory structure), the select transistor layer including backend transistors having a channel composition different than the front end transistors (Par. 42 “[t]he semiconductor substrate 100 can include bulk silicon, bulk silicon-germanium, or semiconductor substrate with silicon or silicon-germanium epitaxial layer” while par. 52 teaches that “the semiconductor layer patterns 202, 204, 206 can be formed with…single crystalline semiconductor” materials and so the select transistor layer channel can include SiGe while the backend transistor channel structure can comprise single crystalline Si), wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (See above annotated fig. 2A semiconductor layer patterns 202/204/206 coupled to bit lines 172).
Lee does not appear to teach
a computing device, comprising:
a board;
a component coupled to the board; and
the memory transistor layer including front end nanowire-based transistors.
Li teaches
the memory transistor layer including front end nanowire-based transistors (Par. 46 “[a] standard vertical nanowire transistor process may be used to form the select transistor for the memory cell and array”).
LaJoie teaches
a board (Fig. 7 integrated circuit die 702); and
a component coupled to the board (Fig. 7 processor 704 coupled to integrated circuit die 702).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee with the teachings of Li as both Lee and Li teach suitable types of transistor for use as select transistor in a memory array, it would have been obvious to substitute Lee’s select transistors with Li’s nanowire-based select transistors to achieve the predictable result of forming nanowire-based select transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lee and Li with the teachings of LaJoie because LaJoie teaches the technique of integrating a memory device, such as the one taught by the combination of Lee and Kajiyama, into a larger computing device as represented by LaJoie’s fig. 7.
Regarding claim 17, the combination of Lee, Li, and LaJoie teaches the computing device of claim 16, further comprising:
a memory coupled to the board (LaJoie fig. 7 on-die memory 706 coupled to integrated circuit die 702. As LaJoie teaches the technique of integrating a device as taught by the combination of Lee and Li into a larger computing device, they also teach the other associated components in fig. 7 which includes a memory coupled to the board).
Regarding claim 18, the combination of Lee, Li, and LaJoie teaches the computing device of claim 16, further comprising:
a communication chip coupled to the board (LaJoie fig. 7 communications chip 708. As LaJoie teaches the technique of integrating a device as taught by the combination of Lee and Li into a larger computing device, they also teach the other associated components in fig. 7 which includes a communication chip coupled to the board).
Regarding claim 19, the combination of Lee, Li, and LaJoie teaches the computing device of claim 16,
wherein the component is a packaged integrated circuit die (LaJoie par. 83 “[t]he processor 704 of the computing device 700 includes one or more devices, such as transistors” and so the processor is a packaged integrated circuit die).
Regarding claim 20, the combination of Lee, Li, and LaJoie teaches the computing device of claim 16,
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (LaJoie fig. 7 processor 704 is a processor).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812