Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section titled “Claim Rejection under 35 U.S.C. 112,” filed 05/13/2026, with respect to the rejection of claims 2 and 7 under 35 U.S.C. 112 have been fully considered and are persuasive. The rejection of claims 2 and 7 under 35 U.S.C. 112 has been withdrawn.
Applicant’s arguments, see section titled “Claim Rejection under 35 U.S.C. 112,” filed 05/13/2026, with respect to the objection to the drawings have been fully considered and are persuasive. The objection to the drawings has been withdrawn.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding amended claim 1, Pan et al. (US20200051607A1, hereinafter Pan) teaches an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (Fig. 3 array of ferroelectric memory cells 306), the plurality of plate lines laterally adjacent to the capacitor array (Fig. 3 upper/lower conductor layers 328/329 are plate lines that are laterally adjacent to array of ferroelectric memory cells 306);
a memory transistor layer beneath the memory structure layer (Fig. 3 transistor 314 is disposed beneath array of ferroelectric memory cells 306), the memory transistor layer coupled to corresponding capacitors of the capacitor array of the memory structure layer (Fig. 3 transistor 314 is disposed beneath and coupled to array of ferroelectric memory cells 306); and
Pan does not appear to teach
the memory transistor layer including front end fin-based transistors
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Kajiyama et al. (US20120008367A1, hereinafter Kajiyama) teaches
the memory transistor layer including front end fin-based transistors (Par. 140 “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics”).
Lee et al. (US20100112753A1, hereinafter Lee) teaches
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (Fig. 1 and par. 64 teaches that logic region 20 comprises “[l]ogic devices such as NMOS or PMOS transistors 110, 112 [which] can be formed in the logic regions 20 on the semiconductor substrate 100” and they are not fin based transistor).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pan with the teachings of Kajiyama because “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics” (Kajiyama par. 140). It would have been obvious to further modify the combination of Pan and Kajiyama with the teachings of Lee because, while Pan discloses that their word lines can be used to select, they do not disclose a specific select transistor structure. This would motivate a person of ordinary skill in the art to seek out references such as Lee who do explicitly teach the select transistor layer structure.
See below for full claims mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (US20200051607A1) in view of Kajiyama (US20120008367A1) and Lee (US20100112753A1).
Regarding claim 1, Pan teaches an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (Fig. 3 array of ferroelectric memory cells 306), the plurality of plate lines laterally adjacent to the capacitor array (Fig. 3 upper/lower conductor layers 328/329 are plate lines that are laterally adjacent to array of ferroelectric memory cells 306);
a memory transistor layer beneath the memory structure layer (Fig. 3 transistor 314 is disposed beneath array of ferroelectric memory cells 306), the memory transistor layer coupled to corresponding capacitors of the capacitor array of the memory structure layer (Fig. 3 transistor 314 is disposed beneath and coupled to array of ferroelectric memory cells 306); and
Pan does not appear to teach
the memory transistor layer including front end fin-based transistors
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Kajiyama teaches
the memory transistor layer including front end fin-based transistors (Par. 140 “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics”).
Lee teaches
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (Fig. 1 and par. 64 teaches that logic region 20 comprises “[l]ogic devices such as NMOS or PMOS transistors 110, 112 [which] can be formed in the logic regions 20 on the semiconductor substrate 100” and they are not fin based transistor).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pan with the teachings of Kajiyama because “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics” (Kajiyama par. 140). It would have been obvious to further modify the combination of Pan and Kajiyama with the teachings of Lee because, while Pan discloses that their word lines can be used to select, they do not disclose a specific select transistor structure. This would motivate a person of ordinary skill in the art to seek out references such as Lee who do explicitly teach the select transistor layer structure.
Regarding claim 2, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 1,
wherein each capacitor of the capacitor array of the memory structure layer has a cylindrical circular shape from the plan view perspective (Pan par. 72 teaches that “[e]ach ferroelectric memory cell 102 can be in a substantially circular shape in the plan view”).
Regarding claim 3, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 1,
wherein the front end fin-based transistors are single crystalline silicon fin-based transistors (Lee teaches the structure for a select transistor layer, see claim 1, and so they also teach their structure. Par. 52 of Lee teaches “the semiconductor layer patterns 202, 204, 206 can be formed with…single crystalline semiconductor” and so they teach a single crystalline transistor. Kojima teaches the use of a finFET, see claim 1, so the combination of Pan, Kajiyama, and Lee teaches wherein the front end fin-based transistors are single crystalline silicon fin-based transistors).
Regarding claim 4, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 1, further comprising:
a second memory structure layer beneath the memory transistor layer (Fig. 3 array of ferroelectric memory cells 304 beneath array of ferroelectric memory cells 306), the second memory structure layer including a second capacitor array coupled to a second plurality of plate lines (Fig. 3 see plurality of plate lines that are laterally adjacent to array of ferroelectric memory cells 304).
Regarding claim 5, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 4,
wherein one or more backend transistors of the select transistor layer is coupled to the second plurality of plate lines of the second memory structure layer (Lee teaches the specific select transistor structure, see claim 1, and so they also teach the technique of having both upper and lower memory arrays 132/282 coupled to the select transistor layer 20 as shown in fig 1).
Regarding claim 6, Pan teaches an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (Fig. 3 array of ferroelectric memory cells 306), the plurality of plate lines laterally adjacent to the capacitor array (Fig. 3 upper/lower conductor layers 328/329 are plate lines that are laterally adjacent to array of ferroelectric memory cells 306);
a memory transistor layer beneath the memory structure layer (Fig. 3 transistor 314 is disposed beneath array of ferroelectric memory cells 306), the memory transistor layer transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer (Fig. 3 transistor 314 is disposed beneath and coupled to array of ferroelectric memory cells 306); and
Pan does not appear to teach
the memory transistor layer including front end nanowire-based transistors,
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end nanowire-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Kajiyama teaches
the memory transistor layer including front end fin-based transistors (Par. 140 “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics”).
Lee teaches
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (Fig. 1 and par. 64 teaches that logic region 20 comprises “[l]ogic devices such as NMOS or PMOS transistors 110, 112 [which] can be formed in the logic regions 20 on the semiconductor substrate 100” and they are not fin based transistor).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pan with the teachings of Kajiyama because “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics” (Kajiyama par. 140). It would have been obvious to further modify the combination of Pan and Kajiyama with the teachings of Lee because, while Pan discloses that their word lines can be used to select, they do not disclose a specific select transistor structure. This would motivate a person of ordinary skill in the art to seek out references such as Lee who do explicitly teach the select transistor layer structure.
Regarding claim 7, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 6,
wherein each capacitor of the capacitor array of the memory structure layer has a circular shape from the plan view perspective (Pan par. 72 teaches that “[e]ach ferroelectric memory cell 102 can be in a substantially circular shape in the plan view”).
Regarding claim 8, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 6,
wherein the front end nanowire-based transistors are single crystalline silicon nanowire-based transistors (Lee teaches the structure for a select transistor layer, see claim 1, and so they also teach their structure. Par. 52 of Lee teaches “the semiconductor layer patterns 202, 204, 206 can be formed with…single crystalline semiconductor” and so they teach a single crystalline transistor. Kojima teaches the use of a finFET, see claim 1, so the combination of Pan, Kajiyama, and Lee teaches wherein the front end fin-based transistors are single crystalline silicon fin-based transistors).
Regarding claim 9, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 6, further comprising:
a second memory structure layer beneath the memory transistor layer (Fig. 3 array of ferroelectric memory cells 304 beneath array of ferroelectric memory cells 306), the second memory structure layer including a second capacitor array coupled to a second plurality of plate lines (Fig. 3 see plurality of plate lines that are laterally adjacent to array of ferroelectric memory cells 304.
Regarding claim 10, the combination of Pan, Kajiyama, and Lee teaches the integrated circuit structure of claim 9,
wherein one or more backend transistors of the select transistor layer is coupled to the second plurality of plate lines of the second memory structure layer (Lee teaches the specific select transistor structure, see claim 1, and so they also teach the technique of having both upper and lower memory arrays 132/282 coupled to the select transistor layer 20 as shown in fig 1).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (US20200051607A1) in view of Kajiyama (US20120008367A1), Lee (US20100112753A1), and LaJoie et al. (US20200098932A1, hereinafter LaJoie).
Regarding claim 11, Pan teaches an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (Fig. 3 array of ferroelectric memory cells 306), the plurality of plate lines laterally adjacent to the capacitor array (Fig. 3 upper/lower conductor layers 328/329 are plate lines that are laterally adjacent to array of ferroelectric memory cells 306);
a memory transistor layer beneath the memory structure layer (Fig. 3 transistor 314 is disposed beneath array of ferroelectric memory cells 306), the memory transistor layer including front end fin-based transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer (Fig. 3 transistor 314 is disposed beneath and coupled to array of ferroelectric memory cells 306).
Pan does not appear to teach
a computing device, comprising:
a board; and
a component coupled to the board,
the memory transistor layer including front end fin-based transistors
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Kajiyama teaches
the memory transistor layer including front end fin-based transistors (Par. 140 “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics”).
Lee teaches
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end fin-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer (Fig. 1 and par. 64 teaches that logic region 20 comprises “[l]ogic devices such as NMOS or PMOS transistors 110, 112 [which] can be formed in the logic regions 20 on the semiconductor substrate 100” and they are not fin based transistor).
Lajoie teaches
a board (Fig. 7 integrated circuit die 702); and
a component coupled to the board (Fig. 7 processor 704 coupled to integrated circuit die 702).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pan with the teachings of Kajiyama because “memory that uses the FinFET for the select transistor can reduce a cell area and improve its operating characteristics” (Kajiyama par. 140). It would have been obvious to further modify the combination of Pan and Kajiyama with the teachings of Lee because, while Pan discloses that their word lines can be used to select, they do not disclose a specific select transistor structure. This would motivate a person of ordinary skill in the art to seek out references such as Lee who do explicitly teach the select transistor layer structure. It would have been obvious to further modify the combination of Pan, Kajiyama, and Lee with the teachings of Lajoie because LaJoie teaches the technique of integrating a memory device, such as the one taught by the combination of Pan, Kajiyama, and Lee into a larger computing device as represented by LaJoie’s fig. 7.
Regarding claim 12, the combination of Pan, Kajiyama, Lee, and Lajoie teaches the computing device of claim 11, further comprising:
a memory coupled to the board (Lajoie fig. 7 volatile memory 710. As LaJoie teaches the technique of integrating a device as taught by the combination of Pan, Kajiyama, and Lee into a larger computing device, they also teach the other associated components in fig. 7 which includes a memory coupled to the board).
Regarding claim 13, the combination of Pan, Kajiyama, Lee, and Lajoie teaches the computing device of claim 11, further comprising:
a communication chip coupled to the board (LaJoie fig. 7 communications chip 708. As LaJoie teaches the technique of integrating a device as taught by the combination of Pan, Kajiyama, and Lee into a larger computing device, they also teach the other associated components in fig. 7 which includes a communication chip coupled to the board).
Regarding claim 14, the combination of Pan, Kajiyama, Lee, and Lajoie teaches the computing device of claim 11,
wherein the component is a packaged integrated circuit die (LaJoie par. 83 “[t]he processor 704 of the computing device 700 includes one or more devices, such as transistors” and so the processor is a packaged integrated circuit die).
Regarding claim 15, the combination of Pan, Kajiyama, Lee, and Lajoie teaches the computing device of claim 11,
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (LaJoie fig. 7 processor 704 is a processor).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (US20200051607A1) in view of Li (US20130270508A1), Lee (US20100112753A1), and LaJoie et al. (US20200098932A1, hereinafter LaJoie).
Regarding claim 16, Pan teaches an integrated circuit structure, comprising:
a memory structure layer including a capacitor array coupled to a plurality of plate lines (Fig. 3 array of ferroelectric memory cells 306), the plurality of plate lines laterally adjacent to the capacitor array (Fig. 3 upper/lower conductor layers 328/329 are plate lines that are laterally adjacent to array of ferroelectric memory cells 306);
a memory transistor layer beneath the memory structure layer (Fig. 3 transistor 314 is disposed beneath array of ferroelectric memory cells 306), the memory transistor layer including transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer (Fig. 3 transistor 314 is disposed beneath and coupled to array of ferroelectric memory cells 306).
Pan does not appear to teach
a board,
a component coupled to the board,
the memory transistor layer including front end nanowire-based transistors, and
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end nanowire-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Li teaches
the memory transistor layer including front end nanowire-based transistors (Par. 46 “[a] standard vertical nanowire transistor process may be used to form the select transistor for the memory cell and array”).
Lee teaches
a select transistor layer over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end nanowire-based transistors, wherein one or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
Lajoie teaches
a board (Fig. 7 integrated circuit die 702),
a component coupled to the board (Fig. 7 processor 704 coupled to integrated circuit die 702).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pan with the teachings of Lee because, while Pan discloses that their word lines can be used to select, they do not disclose a specific select transistor structure. This would motivate a person of ordinary skill in the art to seek out references such as Lee who do explicitly teach the select transistor layer structure. It would have been obvious to further modify the combination of Pan and Lee with the teachings of Li as both Lee and Li teach suitable types of transistor for use as select transistor in a memory array, it would have been obvious to substitute Lee’s select transistors with Li’s nanowire-based select transistors to achieve the predictable result of forming nanowire-based select transistors. It would have been obvious to further modify the combination of Pan, Lee, and Li with the teachings of Lajoie because LaJoie teaches the technique of integrating a memory device, such as the one taught by the combination of Pan, Lee, and Li into a larger computing device as represented by LaJoie’s fig. 7.
Regarding claim 17, the combination of Pan, Lee, Li, and Lajoie teaches the computing device of claim 16, further comprising:
a memory coupled to the board (Lajoie fig. 7 volatile memory 710. As LaJoie teaches the technique of integrating a device as taught by the combination of Pan, Lee, and Li into a larger computing device, they also teach the other associated components in fig. 7 which includes a memory coupled to the board).
Regarding claim 18, the combination of Pan, Lee, Li, and Lajoie teaches the computing device of claim 16, further comprising:
a communication chip coupled to the board (LaJoie fig. 7 communications chip 708. As LaJoie teaches the technique of integrating a device as taught by the combination of Pan, Lee, and Li into a larger computing device, they also teach the other associated components in fig. 7 which includes a memory coupled to the board).
Regarding claim 19, the combination of Pan, Lee, Li, and Lajoie teaches the computing device of claim 16,
wherein the component is a packaged integrated circuit die (LaJoie par. 83 “[t]he processor 704 of the computing device 700 includes one or more devices, such as transistors” and so the processor is a packaged integrated circuit die).
Regarding claim 20, the combination of Pan, Lee, Li, and Lajoie teaches the computing device of claim 16,
wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (LaJoie fig. 7 processor 704 is a processor).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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