DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haratipour et al. (US 20210408018 A1, hereinafter 018)
With regards to claim 1, 018 discloses an integrated circuit structure, (FIGS. 5, 7, and 8) comprising:
a plurality of plate lines (electrodes 502a/b and 504a/b, see FIGS. 5 and 7) along a first direction; (up and down the page of FIG. 5/7)
a transistor ( transistor 701) beneath the plurality of plate lines, with a direction of a first source or drain (source 706) to a gate (gate 703) to a second source or drain (drain 704) of the transistor being a second direction orthogonal to the first direction; (left to right of the page of FIG. 5/7) and
a plurality of capacitor structures (capacitor structure comprising electrodes 506, dielectric 507, and portions of 502/504 in direct contact with dielectric 507) over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines, (see FIGS. 5 and 7)
wherein the plurality of capacitor structures has a staggered arrangement from a plan view perspective. (See FIGS. 5 and 7, showing the staggered/jagged structure of the capacitors) and the individual ones of the plurality of capacitor structures are in a same horizontal plane. (See annotated FIG. 5, where the “horizontal” plane is in a direction perpendicular to a top surface of the substrate, see also Response to Arguments.)
With regards to claim 2, 018 discloses the integrated circuit structure of claim 1, wherein each of the plurality of capacitor structures has a cylindrical shape from the plan view perspective. (See at least FIGS. 5,7 and paragraph [0170], where the electrodes are cylindrical)
With regards to claim 3, 018 discloses the integrated circuit structure of claim 1, wherein the transistor is a planar transistor. (See FIG. 7)
With regards to claim 4, 018 discloses the integrated circuit structure of claim 1, wherein the transistor is a fin-based transistor. (Paragraph [0173]: “Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors.”)
With regards to claim 6, 018 discloses an integrated circuit structure, (FIGS. 5, 7, and 8) comprising:
a plurality of stacks of plate lines (electrodes 502a/b and 504a/b, see FIGS. 5 and 7) comprising a first vertical stack of plate lines, (electrode 504a) a second vertical stack of plate lines (electrode 502b) inset from the first vertical stack of plate lines from a cross-sectional perspective, and a third vertical stack of plate lines (right portion of electrode 504b) inset from the second vertical stack of plate lines from the cross-sectional perspective; (See FIGS. 5 and 7)
a transistor structure ( transistor 701) below the plurality of stacks of plate lines; and
a plurality of capacitor structures (capacitor structure comprising electrodes 506, dielectric 507, and portions of 502/504 in direct contact with dielectric 507) coupled to the plurality of stacks of plate lines, the plurality of capacitor structures comprising a first capacitor structure (capacitor structure comprising electrodes 506c, dielectric 507, and portions of 502b in direct contact with dielectric 507) coupled to the first vertical stack of plate lines, a second capacitor structure (capacitor structure comprising electrodes 506d, dielectric 507, and portions of 504a in direct contact with dielectric 507) inset from the first capacitor structure from the cross-sectional perspective and coupled to the second vertical stack of plate lines, and a third capacitor structure (capacitor structure comprising electrodes 506e, dielectric 507, and portions of 504b in direct contact with dielectric 507) inset from the second capacitor structure from the cross-sectional perspective and coupled to the third vertical stack of plate lines. (see FIGS. 5 and 7)
With regards to claim 7, 018 discloses the integrated circuit structure of claim 6, wherein each of the plurality of capacitor structures has a cylindrical shape from the plan view perspective. (See at least FIGS. 5,7 and paragraph [0170], where the electrodes are cylindrical)
With regards to claim 8, 018 discloses the integrated circuit structure of claim 6, wherein the transistor is a planar transistor. (See FIG. 7)
With regards to claim 9, 018 discloses the integrated circuit structure of claim 6, wherein the transistor is a fin-based transistor. (Paragraph [0173]: “Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors.”)
With regards to claim 11, 018 discloses an computing device, (FIGS. 5, 7, and 8) comprising:
a board; (board of computing device 800) and
a component (processor, 801, which is an integrated circuit, see paragraph [0185]) coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of plate lines (electrodes 502a/b and 504a/b, see FIGS. 5 and 7) along a first direction; (up and down the page of FIG. 5/7)
a transistor ( transistor 701) beneath the plurality of plate lines, with a direction of a first source or drain (source 706) to a gate (gate 703) to a second source or drain (drain 704) of the transistor being a second direction orthogonal to the first direction; (left to right of the page of FIG. 5/7) and
a plurality of capacitor structures (capacitor structure comprising electrodes 506, dielectric 507, and portions of 502/504 in direct contact with dielectric 507) over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines, (see FIGS. 5 and 7)
wherein the plurality of capacitor structures has a staggered arrangement from a plan view perspective, (See FIGS. 5 and 7, showing the staggered/jagged structure of the capacitors)
the individual ones of the plurality of capacitor structures are in a same horizontal plane. (See annotated FIG. 5, where the “horizontal” plane is in a direction perpendicular to a top surface of the substrate, see also Response to Arguments.)
With regards to claim 12, 018 discloses the computing device of claim 11, further comprising:
a memory (DRAM 807, see FIG. 8) coupled to the board.
With regards to claim 13, 018 discloses the computing device of claim 11, further comprising:
a communication chip (communication chip 804, see FIG. 8) coupled to the board.
With regards to claim 14, 018 discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die. (processor, 801, which is an integrated circuit, see paragraph [0185])
With regards to claim 15, 018 discloses the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. (processor, 801, which is an integrated circuit, see paragraph [0185])
With regards to claim 16, 018 discloses a computing device, (FIGS. 5, 7, and 8) comprising:
a board; (board of computing device 800) and
a component (processor, 801, which is an integrated circuit, see paragraph [0185]) coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of stacks of plate lines (electrodes 502a/b and 504a/b, see FIGS. 5 and 7) comprising a first vertical stack of plate lines, (electrode 504a) a second vertical stack of plate lines (electrode 502b) inset from the first vertical stack of plate lines from a cross-sectional perspective, and a third vertical stack of plate lines (right portion of electrode 504b) inset from the second vertical stack of plate lines from the cross-sectional perspective; (See FIGS. 5 and 7)
a transistor structure ( transistor 701) below the plurality of stacks of plate lines; and
a plurality of capacitor structures (capacitor structure comprising electrodes 506, dielectric 507, and portions of 502/504 in direct contact with dielectric 507) coupled to the plurality of stacks of plate lines, the plurality of capacitor structures comprising a first capacitor structure (capacitor structure comprising electrodes 506c, dielectric 507, and portions of 502b in direct contact with dielectric 507) coupled to the first vertical stack of plate lines, a second capacitor structure (capacitor structure comprising electrodes 506d, dielectric 507, and portions of 504a in direct contact with dielectric 507) inset from the first capacitor structure from the cross-sectional perspective and coupled to the second vertical stack of plate lines, and a third capacitor structure (capacitor structure comprising electrodes 506e, dielectric 507, and portions of 504b in direct contact with dielectric 507) inset from the second capacitor structure from the cross-sectional perspective and coupled to the third vertical stack of plate lines, (see FIGS. 5 and 7)
wherein the first, second, and third capacitor structures are in a same horizontal plane. (See annotated FIG. 5, where the “horizontal” plane is in a direction perpendicular to a top surface of the substrate, see also Response to Arguments.)
With regards to claim 17, 018 discloses the computing device of claim 16, further comprising: a memory (DRAM 807, see FIG. 8) coupled to the board.
With regards to claim 18, 018 discloses the computing device of claim 16, further comprising:
a communication chip (communication chip 804, see FIG. 8) coupled to the board.
With regards to claim 19, 018 discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die. (processor, 801, which is an integrated circuit, see paragraph [0185])
With regards to claim 20, 018 discloses the computing device of claim 16, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. (processor, 801, which is an integrated circuit, see paragraph [0185])
Allowable Subject Matter
Claims 5 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-22 are allowed.
Response to Arguments
Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive.
Examiner notes that “horizontal plane” is a relative term. The “horizontal plane” is based on which direction the device is oriented. In other words, if the device is oriented such that the top surface of the substrate is perpendicular to the ground, then a “horizontal plane” is one that is similar to that which is shown in annotated FIG. 5. Since Applicant has not defined the term “horizontal” in the Specification or the claims, and Applicant has not tied “horizontal” to the device itself, Examiner can interpret “horizontal plane” to be “ a plane that is perpendicular to a top surface of the substrate.” Therefore, claims 1, 11, and 16 are rejected, and claims 2-4, 6-9, 12-15, and 17-20 are rejected for at least their dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Frougier et al. (US 20200287046 A1) – general nanowire FET
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
Prosecution Insights