DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Petti (US 2023/0077181).
Regarding claim 1, Petti discloses, in at least figure 1 and related text, an integrated circuit structure, comprising:
a stack of alternating dielectric layers (15/17(17a/17b), [38], [42]) and metal layers (16(16a/16b)/18, [38], [42]);
a trench (22, trench for 25/26/28, [39], [42]) through the stack of alternating dielectric layers (15/17(17a/17b), [38], [42]) and metal layers (16(16a/16b)/18, [38], [42]);
a semiconductor channel layer (25, [39], [42]) along sides and a bottom of the trench (22, trench for 25/26/28, [39], [42]);
a gate dielectric layer (26, [39], [42]) along sides and on a bottom of the semiconductor channel layer (25, [39], [42]) in the trench (22, trench for 25/26/28, [39], [42]); and
a gate electrode (28, [39], [42]) within sides and on a bottom of the gate dielectric layer (26, [39], [42]).
Regarding claim 3, Petti discloses the integrated circuit structure of claim 1 as described above.
Petti further discloses, in at least figure 1 and related text, the gate electrode (28, [39], [42]) is accessible for electrical contact from a top side of the stack of alternating dielectric layers (15/17(17a/17b), [38], [42]) and metal layers (16(16a/16b)/18, [38], [42]) (figure).
Regarding claim 5, Petti discloses the integrated circuit structure of claim 1 as described above.
Petti further discloses, in at least figure 1 and related text, the semiconductor channel layer (25, [39], [42]) is selected from the group consisting of poly-silicon, non-crystalline silicon, germanium, a group III-V material, MoS2, WSe2, MoS2, WSe2, InS, HfS, ZnS, ZnSe, In203, ZnO, AZO, IGZO ([42]), and IZO.
Claim(s) 6-8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2020/0357821).
Regarding claim 6, Chen discloses, in at least figures 4i (i)-(ii) and related text, an integrated circuit structure, comprising:
a stack of alternating dielectric layers (403/405, [44]) and metal layers (419, [50]);
a trench (trench for 409/410/411/412/413, figures) through the stack of alternating dielectric layers (403/405, [44]) and metal layers (419, [50]);
a semiconductor channel layer (409, [46]) along sides and not along a bottom of the trench (trench for 409/410/411/412/413, figures);
a gate dielectric layer (410/411, [46], [47]) along sides of the semiconductor channel layer (409, [46]) and not along a bottom of the trench (trench for 409/410/411/412/413, figures); and
a gate electrode (412/413, [48]) within sides of the gate dielectric layer (410/411, [46], [47]).
Regarding claim 7, Chen discloses the integrated circuit structure of claim 6 as described above.
Chen further discloses, in at least figures 4i (i)-(ii) and related text, an uppermost layer of the stack of alternating dielectric layers (403/405, [44]) and metal layers (419, [50]) is a dielectric layer (405, [44]), and the semiconductor channel layer (409, [46]) extends into the top dielectric layer (405, [44]) (figure).
Regarding claim 8, Chen discloses the integrated circuit structure of claim 6 as described above.
Chen further discloses, in at least figures 4i (i)-(ii) and related text, the gate electrode (412/413, [48]) is accessible for electrical contact from a bottom side of the stack of alternating dielectric layers (403/405, [44]) and metal layers (419, [50]).
Regarding claim 10, Chen discloses the integrated circuit structure of claim 6 as described above.
Chen further discloses, in at least figures 4i (i)-(ii) and related text, the semiconductor channel layer (409, [46]) is selected from the group consisting of poly-silicon ([46]), non-crystalline silicon, germanium, a group III-V material, MoS2, WSe2, MoS2, WSe2, InS, HfS, ZnS, ZnSe, In203, ZnO, AZO, IGZO, and IZO.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0403033) in view of Petti (US 2023/0077181).
Regarding claim 11, Lilak discloses, in at least figures 15D, 16, and related text, a computing device, comprising:
a board (402, [74]); and
a component (404, [77]) coupled to the board (402, [74]), the component (404, [77]) including an integrated circuit structure ([77]), comprising:
a stack of alternating dielectric layers (115, [45]) and metal layers (116, [45], [56]);
a trench (trench for 120, [38], figures) through the stack of alternating dielectric layers (115, [45]) and metal layers (116, [45], [56]).
Lilak does not explicitly disclose a semiconductor channel layer along sides and a bottom of the trench; a gate dielectric layer along sides and on a bottom of the semiconductor channel layer in the trench; a gate electrode within sides and on a bottom of the gate dielectric layer.
Petti teaches, in at least figure 1 and related text, the device comprising a semiconductor channel layer (25, [39], [42]) along sides and a bottom of the trench (22, trench for 25/26/28, [39], [42]); a gate dielectric layer (26, [39], [42]) along sides and on a bottom of the semiconductor channel layer (25, [39], [42]) in the trench (22, trench for 25/26/28, [39], [42]); a gate electrode (28, [39], [42]) within sides and on a bottom of the gate dielectric layer (26, [39], [42]), for the purpose of providing multiple stacks of thin-film ferroelectric field-effect transistors (FeFETs) being organized as multiple stacks of NOR memory strings extending along a first direction substantially parallel to the planar surface of the semiconductor substrate ([9]) thereby improving density of integration.
Lilak and Petti are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Petti because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the semiconductor channel layer along sides and a bottom of the trench; the gate dielectric layer along sides and on a bottom of the semiconductor channel layer in the trench; the gate electrode within sides and on a bottom of the gate dielectric layer, as taught by Petti, for the purpose of providing multiple stacks of thin-film ferroelectric field-effect transistors (FeFETs) being organized as multiple stacks of NOR memory strings extending along a first direction substantially parallel to the planar surface of the semiconductor substrate ([9], Petti) thereby improving density of integration.
Regarding claim 12, Lilak in view of Petti discloses the computing device of claim 11 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, a memory ([75]) coupled to the board (402, [74]).
Regarding claim 13, Lilak in view of Petti discloses the computing device of claim 11 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, a communication chip (406, [76]) coupled to the board (402, [74]).
Regarding claim 14, Lilak in view of Petti discloses the computing device of claim 11 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, the component (404, [77]) is a packaged integrated circuit die ([77]).
Regarding claim 15, Lilak in view of Petti discloses the computing device of claim 11 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, the component (404, [77]) is selected from the group consisting of a processor ([77]), a communications chip, and a digital signal processor.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0403033) in view of Chen (US 2020/0357821).
Regarding claim 16, Lilak discloses, in at least figures 15D, 16, and related text, a computing device, comprising:
a board (402, [74]); and
a component (404, [77]) coupled to the board (402, [74]), the component (404, [77]) including an integrated circuit structure ([77]), comprising:
a stack of alternating dielectric layers (115, [45]) and metal layers (116, [45], [56]);
a trench (trench for 120, [38], figures) through the stack of alternating dielectric layers (115, [45]) and metal layers (116, [45], [56]).
Lilak does not explicitly disclose a semiconductor channel layer along sides and not along a bottom of the trench; a gate dielectric layer along sides of the semiconductor channel layer and not along a bottom of the trench; a gate electrode within sides of the gate dielectric layer.
Chen teaches, in at least figures 4i (i)-(ii) and related text, the device comprising a semiconductor channel layer (409, [46]) along sides and not along a bottom of the trench (trench for 409/410/411/412/413, figures); a gate dielectric layer (410/411, [46], [47]) along sides of the semiconductor channel layer (409, [46]) and not along a bottom of the trench (trench for 409/410/411/412/413, figures); a gate electrode (412/413, [48]) within sides of the gate dielectric layer (410/411, [46], [47]), for the purpose of providing a 3-dimensional vertical memory string array that includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications ([17]).
Lilak and Chen are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the semiconductor channel layer along sides and not along a bottom of the trench; the gate dielectric layer along sides of the semiconductor channel layer and not along a bottom of the trench; the gate electrode within sides of the gate dielectric layer, as taught by Chen, for the purpose of providing a 3-dimensional vertical memory string array that includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications ([17], Chen).
Regarding claim 17, Lilak in view of Chen discloses the computing device of claim 16 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, a memory ([75]) coupled to the board (402, [74]).
Regarding claim 18, Lilak in view of Chen discloses the computing device of claim 16 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, a communication chip (406, [76]) coupled to the board (402, [74]).
Regarding claim 19, Lilak in view of Chen discloses the computing device of claim 16 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, the component (404, [77]) is a packaged integrated circuit die ([77]).
Regarding claim 20, Lilak in view of Chen discloses the computing device of claim 16 as described above.
Lilak further discloses, in at least figures 15D, 16, and related text, the component (404, [77]) is selected from the group consisting of a processor ([77]), a communications chip, and a digital signal processor.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 2 that recite "the semiconductor channel layer extends along a top of the top dielectric layer" in combination with other elements of the base claims 1 and 2.
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 4 that recite "the metal layers include successive drain layers above successive source layers" in combination with other elements of the base claims 1 and 4.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 6 and 9 that recite "the metal layers include successive drain layers above successive source layers" in combination with other elements of the base claims 6 and 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811