The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of the embodiment of figure 1 in the reply filed on 07/20/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. (10,522,510).Regarding claims 1, 6, 11 and 16, Jun et al. teach in figure 7 and related text an integrated circuit structure, comprising:
a first die 1010 (see figure 1 for numerals) comprising a first device layer 200, a first plurality of metallization layers over the first device layer, and
a first conductive interconnection 250 over the first plurality of metallization layers; and
a second device layer (the left side of layer 200), a second plurality of metallization layers (in the left side of layer 200) over the second device layer, and a second conductive interconnection (the left side of layer 250), over the second plurality of metallization layers,
Jun et al. do not teach in figure 7 a second die separated from the first die by a scribe region.
Jun et al. teach in figure 1 and related text a second die 1020 separated from the first die 1010 by a scribe region 125.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a second die separated from the first die by a scribe region, as taught by the embodiment of figure 1 of Jun et al., in the embodiment of figure 7 of Jun et al., in order to reduce the size of the device by forming two dies on one substrate.
In the combined device, the second conductive interconnection (the left side of layer 250) extending over the scribe region and coupled to the first conductive interconnection.
Regarding claims 2 and 7, Jun et al. teach in figure 7 and related text that the first conductive interconnection (the right side of layer 250) is coupled to the first plurality of metallization layers of the first die by a first via stack (on the right side) of the first die, and the second conductive interconnection (the left side of layer 250) is coupled to the second plurality of metallization layers of the second die by a second via stack (on the left side) of the second die.
Regarding claims 3-5 and 8-10, Jun et al. do not teach in figure 7 and related text that the first device layer and the second device layer are both logic device layers, or are both SRAM device layers.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first device layer and the second device layer are both logic device layers, or are both SRAM device layers, and the first device layer is a logic device layer, and the second device layer is an SRAM device layer, and the first device layer is an SRAM device layer, and the second device layer is a logic device layer in Jun et al.’s device, in order to expand the applicability of the device.
Regarding claims 6 and 16, Jun et al. teach in figure 7 and related text a third conductive interconnection (the middle of element 250) extending over the scribe region (in the combined device) and coupled to the first conductive interconnection and the second conductive interconnection.
Regarding claim 11, Jun et al. teach in figure 10 and related text a board; and a component coupled to the board, the component including an integrated circuit structure.
Regarding claims 12-15 and 17-20, Jun et al. do not teach in figure 7 and related text a memory coupled to the board, and a communication chip coupled to the board, and a battery coupled to the board, and wherein the component is a packaged integrated circuit die.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a memory coupled to the board, and a communication chip coupled to the board, and a battery coupled to the board, and wherein the component is a packaged integrated circuit die in Jun et al.’s device, in order to expand the applicability of the device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
7/30/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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