Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1 is rejected under 35 U.S.C. 103 as being unpatentable over Gregorich (US Patent No. 9437512).
Regarding claim 1, Gregorich teaches a semiconductor package comprising: a package substrate comprising a first mounting region and a second mounting region at a top surface of the package substrate; a first semiconductor chip disposed on the first mounting region of the package substrate; a second semiconductor chip disposed on the second mounting region of the package substrate (Fig. 3 points to an IC package structure comprising a PCB 201 (package substrate), a semiconductor chip 283 (first semiconductor chip), and a semiconductor chip 253 (second semiconductor chip).); an interposer substrate disposed on the second mounting region of the package substrate and covering the second semiconductor chip (Id. points to a package substrate 261 (interposer substrate).); a plurality of conductive connectors extending from a bottom surface of the interposer substrate to the top surface of the package substrate and laterally spaced apart from the second semiconductor chip (Id. points to a plurality of solder balls 257 and 267 (conductive connectors).); and a third semiconductor chip on a top surface of the interposer substrate (Id. points to a semiconductor chip 263 (third semiconductor chip).), wherein a first distance between a top surface of the first semiconductor chip and the top surface of the package substrate is greater than a second distance between the top surface of the interposer substrate and the top surface of the package substrate (Fig. 3 points to the IC package 280, comprising the semiconductor chip 283 (first semiconductor chip), with no other components formed above. In light of this, it is considered obvious that the height of said chip 283 could be increased to at least be higher than the package substrate 261 (interposer substrate) in order to increase chip density and/or improve performance.), and wherein the plurality of conductive connectors electrically connect the interposer substrate to the package substrate (Fig. 3 and Col. 3, lines 29-63 to a plurality of solder balls 257 and 267 (conductive connectors), which allow for electrical communication between the package substrate 261 (interposer substrate) and the PCB 201 (package substrate).).
Regarding claim 3, Gregorich teaches wherein the second distance between the top surface of the interposer substrate and the top surface of the package substrate is 200 µm or less, and wherein the first distance between the top surface of the first semiconductor chip and the top surface of the package substrate is selected from a range of 200 µm to 1,000 µm (Fig. 3 points to the PCB 201 (package substrate), the package substrate 261 (interposer substrate), and the semiconductor chip 283 (first semiconductor chip), which has no other components above it. In light of this, it is considered obvious that the height of said chip 283 could be increased to at least be higher than the package substrate 261 (interposer substrate) in order to increase chip density and/or improve performance. Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).).
Regarding claim 4, Gregorich teaches wherein a third distance between a top surface of the second semiconductor chip and the top surface of the package substrate is 100 µm or less (Fig. 3 points to the semiconductor chip 253 (second semiconductor chip) and the PCB 201 (package substrate). Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).).
Claim(s) ___ are rejected under 35 U.S.C. 103 as being unpatentable over Gregorich in further view of Lee (PGPub No. 20220020664).
Regarding claim 8, Lee teaches a heat sink covering the top surface of the first semiconductor chip (Fig. 1A points to a heat dissipation unit 950 (heat sink) positioned above the second semiconductor device 200 (first semiconductor chip).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Gregorich and Lee, such that a heat sink/dissipation unit is positioned over the first semiconductor chip in order to provide cooling and allow for adequate heat dissipation.
Regarding claim 9, Lee teaches a molding layer including a first portion surrounding sidewalls of the first semiconductor chip without covering the top surface of the first semiconductor chip, wherein a top surface of the molding layer is coplanar with the top surface of the first semiconductor chip (Fig. 3 and [0075-76] point to an alternative embodiment of the second semiconductor device 200 (first semiconductor chip) encapsulated by a molding layer 230 (first portion) that leaves the top surface of said device exposed.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich and Lee, such that a molding layer is further formed around the first semiconductor chip while leaving the top surface exposed in order to balance physical stability and/or protection from external forces with heat dissipation.
Regarding claim 10, Gregorich in combination with Lee teaches wherein the molding layer further comprises a second portion that is disposed between the bottom surface of the interposer substrate and each of the top surface of the package substrate and a top surface of the second semiconductor chip, and wherein the second portion contacts the second semiconductor chip and each conductive conductor of the plurality of conductive connectors (Fig. 3 of Gregorich points to the package substrate 261 (interposer substrate), the PCB 201 (package substrate), the semiconductor chip 253 (second semiconductor chip), and the plurality of solder balls 257 and 267 (conductive connectors). Figs. 1A-1B and [0045] of Lee further points to a package molding layer 800 (second portion) on the first substrate 300/300a (package substrate) that may also extend laterally.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich and Lee, such that the molding layer further comprises a second portion that extends laterally underneath the interposer substrate and around the second semiconductor chip in order to further protect said chip as well as the connection(s) between the interposer and package substrates.
Regarding claim 11, Lee teaches wherein the molding layer does not cover the top surface of the interposer substrate (Fig. 1B points to the first semiconductor device 100 comprising a second protective insulating layer 125 (interposer substrate) and a molding layer 130.).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in further view of Arguin (US Patent No. 10784202).
Regarding claim 2, Arguin teaches wherein the top surface of the first semiconductor chip is exposed to the outside of the semiconductor package (Fig. 1 points to an IC package comprising an exposed first die 101 (first semiconductor chip).), and wherein the first width of the interposer substrate is greater than a second width of the second semiconductor chip. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich et al. and Arguin, such that at least the top surface of the first semiconductor chip is left exposed in order to lower costs, create a lower package profile, and/or maintain direct access to the chip.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Gregorich et al. in further view of Loo (US Patent No. 10153253).
Regarding claim 5, Loo teaches a first passive device disposed on the second mounting region of the package substrate, and a second passive device attached to the bottom surface of the interposer substrate (Fig. 6 points to a passive device 652 (first passive device), and a passive device 154 (second passive device).), wherein the first passive device and the second passive device are disposed in a space defined by the bottom surface of the interposer substrate, a sidewall of the second semiconductor chip, and a sidewall of one of the plurality of conductive connectors adjacent to the sidewall of the second semiconductor chip (Id. points to a package substrate 110 (interposer substrate), an active device 650 (second semiconductor chip), and a bump array 160 (plurality of conductive connectors). It is considered obvious that the components of Fig. 6 could be rearranged to better optimize the defined space, such that, for example, the active device 650 is mounted to the bottom land side board 640 (package substrate) and moved to either side such that the passive devices 652 and 154 are located adjacent to the same sidewall of said active device.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich et al. and Loo, such that two passive devices are further formed between the package and interposer substrates in order to improve electrical performance while optimizing use of the space provided.
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Gregorich et al. in further view of Gogineni (PGPub No. 20180190776).
Regarding claim 6, Gogineni teaches a passive device attached to a bottom surface of the package substrate; and an external connection terminal attached to the bottom surface of the package substrate, wherein a distance between a lowermost end of the passive device and the bottom surface of the package substrate is less than a distance between a lowermost end of the external connection terminal and the bottom surface of the package substrate (Fig. 1 and 4C point to an electronic component 16 (third passive device) and solder balls 48 (external connection terminal) mounted to a substrate 12 (package substrate).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich et al. and Gogineni, such that an additional passive device and external connection terminal are attached to the bottom surface of the package substrate in order to improve electrical performance while optimizing use of the space provided.
Regarding claim 7, Lee teaches wherein the first semiconductor chip comprises a logic chip ([0033] points to a second semiconductor device 200 (first semiconductor chip), which may include a CPU chip, a GPU chip, or an AP chip.), and wherein the third semiconductor chip comprises a memory chip ([0027] points to a second semiconductor chip(s) 120 (third semiconductor chip), which may include a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip.), and wherein a horizontal width of the first semiconductor chip is greater than a horizontal width of the second semiconductor chip and a horizontal width of the third semiconductor chip (It is considered obvious that one of ordinary skill in the art could alter the widths of each chip accordingly in order to better optimize the space provided and/or improve the performance of the device as a whole. Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich et al. and Lee, such that the first and third semiconductor chips are a logic chip and memory chip, respectively, in order to optimize the given space within the device by integrating multiple systems/functions.
Gregorich et al. fails to teach wherein the second semiconductor chip comprises at least one of a power management integrated circuit chip and a radio frequency integrated circuit chip.
Gogineni teaches wherein the second semiconductor chip comprises at least one of a power management integrated circuit chip and a radio frequency integrated circuit chip ([0022] points to NAND memory stack 14 comprised of individual silicon dies 15, with suitable silicon dies including a central processing unit, a flash memory, a wireless charger, a power management integrated circuit (PMIC), a Wi-Fi transmitter, and a global positioning system.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Gregorich et al. and Gogineni, such that the stack formed by the second and third semiconductor chips comprises a PMIC chip and a flash memory chip, respectively, in order to optimize power delivery and/or provide a more simplified board design.
Response to Arguments
Applicant’s arguments, see Remarks, filed 10/31/2025, with respect to the rejection of claim 6 under 35 U.S.C. §112(b) have been fully considered and are persuasive. The rejection of said claim has been withdrawn.
Applicant's arguments filed 10/31/2025 with regards to amended claims 12 and 16 (along with any dependent claims) have been fully considered but they are not persuasive. Specifically, Applicant argues that the amendments made to claims 12 and 16, in particular the addition of “wherein the plurality of conductive connectors electrically connect the interposer substrate to the package substrate”, places each claim in a position that overcomes the previous election/restriction requirement (see Office Action dated 06/20/2025). Examiner argues that the amendment(s) made do not address the issues of the previous restriction: claim 16 was subjected to a restriction requirement under Invention II (claims 16-20), which was shown as failing to disclose both “a molding layer” and “a first and second underfill layer” as disclosed in Invention I (claims 1-15), while claim 12 was subjected to an election requirement under Species II (claims 12-15), which was shown to recite mutually exclusive characteristics from Species I (claims 1-11) by uniquely reciting “a first and second underfill layer” while also failing to recite the second portion of the molding layer as disclosed in Species I. For these reasons, Applicant’s arguments are considered unpersuasive and fail to overcome the previous election/restriction requirement; only claims 1-11 will be discussed in this action.
Applicant’s arguments, see Remarks, filed 10/31/2025, with respect to the rejection(s) of claim(s) 1-11 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in further view of newly found prior art Gregorich (US Patent No. 9437512) and Loo (US Patent No. 10153253).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899