Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/26 has been entered.
Applicant's amendment/arguments filed on 06/02/26 as being acknowledged and entered. By this amendment claims 6, and 11-19 are canceled, claim 26 has been added, and claims 1-5, 7-10, and 20-26 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 7, 23-24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueda et al. (WO 2021/167639).
Claim 1: Ueda teaches (Fig. 10C) three-dimensional (3D) memory, comprising: a stack including alternately stacked first dielectric layers (32) and conductive layers (44); and a channel structure (60) extending through the stack and including a second dielectric layer (44) and a blocking layer (52) disposed in this order from outside to inside that cover vertical surfaces of the first dielectric layers and vertical surfaces of the conductive layers directly, the blocking layer further comprises (Fig. 10C): first blocking portions located on a first portion of the second dielectric layer that covers the vertical surfaces of the first dielectric layers: and second blocking portions located on a second portion of the second dielectric layer that covers the vertical surfaces of the conductive layers. wherein the first blocking portions have a thickness larger than that of the second blocking portions in the direction parallel with the first dielectric layers.
Claim 5: Ueda teaches (Fig. 10C) the second dielectric layer further comprises: first dielectric portions extending in the direction of thickness of the stack; and second dielectric portions extending in the direction parallel with the first dielectric layers, wherein the first dielectric portions are in contact with respective second dielectric portions.
Claim 7: Ueda teaches (Fig. 10C) wherein the channel structure further comprises a storage layer (53), a tunneling layer (56) and a channel layer (60) disposed in this order from outside to inside with the storage layer being located on a surface of the blocking layer away from the second dielectric layer.
Claim 23: Ueda teaches (Fig. 10C) the second dielectric layer further comprises: first dielectric portions extending in the direction of thickness of the stack and second dielectric portions extending in the direction parallel with the first dielectric layers, wherein the first dielectric portions are in contact with respective second dielectric portions.
Claim 24: Ueda teaches (Fig. 10C) wherein the channel structure further comprises a storage layer (53), a tunneling layer (56) and a channel layer (60) disposed in this order from outside to inside with the storage layer being located on a surface of the blocking layer away from the second dielectric layer.
Claim 26: Ueda teaches (Fig. 10C) three-dimensional (3D) memory, comprising: a stack including alternately stacked first dielectric layers and conductive layers; and a channel structure extending through the stack and including a second dielectric layer and a blocking layer disposed in this order from outside to inside that cover vertical surfaces of the first dielectric layers and vertical surfaces of the conductive layers, wherein the blocking layer further comprises: first blocking portions located on a first portion of the second dielectric layer that covers the vertical surfaces of the first dielectric layers; and second blocking portions located on a second portion of the second dielectric layer that covers the vertical surfaces of the conductive layers, wherein the first blocking portions have a thickness larger than that of the second blocking portions in the direction parallel with the first dielectric layers, wherein the channel structure further comprises a storage layer (53), a tunneling layer (56) and a channel layer (60) disposed in this order from outside to inside with the storage layer being located on a surface of the blocking layer away from the second dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda et al. (WO 2021/167639), as applied to claims 1 and 9 above, and further in view of Kai et al. (US PGPub 2021/0335805).
Regarding claims 2 and 20, as described above, Ueda substantially reads on the invention as claimed, except Ueda does not teach the second dielectric layer has a dielectric constant greater than or equal to 3.9. Kai teaches (Fig. 9E) the second dielectric layer has a dielectric constant greater than or equal to 3.9. Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was made to substitute one know element for another known element resulting in the predictable result the appropriate dielectric properties needed for the application (KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007)).
Regarding claims 8 and 25, as described above, Ueda substantially reads on the invention as claimed, except Ueda does not teach the dielectric constant of the second dielectric layer is greater than or equal to 10. Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was made to substitute one know element for another known element resulting in the predictable result the appropriate dielectric properties needed for the application (KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007)).
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda et al. (WO 2021/167639).
Claim 9: Ueda teaches memory system, comprising: the 3D memory of claim 1; and a memory controller coupled to the 3D memory and configured to control the 3D memory. Pairing controllers with memory structures in common in the memory art.
Claim 10: Ueda teaches a solid state drive or a memory card. Solid state drives and memory cards are well known in the memory art.
Allowable Subject Matter
Claims 3-4 and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-10 and 20-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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