DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 12/08/2025 has been entered. Claims 1-6, 9-12 and newly added claims 21-28, remain pending in the application. Applicant’s amendments have overcome each and every claim objection and 112(b) rejections previously set forth in the Non-Final Office Action mailed on 09/18/2025.
Claim Objections
Claim 3 is objected to because of the following informalities: “the first direction and the one or more second stop structures” should read “the first direction and the two or more second stop structure.
Claim 22 is objected to because of the following informalities: “the first direction and the one or more second stop structures” should read “the first direction and the two or more second stop structure.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, the claim recites the limitation “the dummy structures are arranged side-by-side along a second direction”. Claim 1, on which claim 6 depends on, recites the limitation “one or more dummy structures”. Therefore, the 3D memory device may comprise only one dummy structure, which cannot satisfy the above limitation of claim 6. For the purpose of examination, claim 6 will be interpreted as: The 3D memory device of claim 1, comprising two or more dummy structures, wherein the two or more dummy structures are arranged side-by-side along a second direction in which the stop structures extend, wherein the second direction is perpendicular to the first direction.
Regarding claim 25, the claim recites the limitation “the dummy structures are arranged side-by-side along a second direction”. Claim 12, on which claim 25 depends on, recites the limitation “one or more dummy structures”. Therefore, the system may comprise only one dummy structure, which cannot satisfy the above limitation of claim 25. For the purpose of examination, claim 25 will be interpreted as: The system of claim 12, comprising two or more dummy structures wherein the two or more dummy structures are arranged side-by- side along a second direction in which the stop structures extend, wherein the second direction is perpendicular to the first direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6 and 9-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shimomura et al., (United States Patent Application Publication Number, US 2022/0302146 A1), hereinafter referenced as Shimomura.
Regarding claim 1, Shimomura teaches a three-dimensional (3D) memory device, comprising: a semiconductor layer (Fig.1D, element #110); a stack structure on the semiconductor layer (Fig.1D, formed by all the elements in the figure), wherein the stack structure comprises alternating conductive layers (Fig.1D, elements #146 and #246) and first dielectric layers (Fig.1D, elements #132, #232, and #232’) and has a core region (Fig.1D, element #100) and a staircase region adjacent to the core region (Fig.1D, element #200); one or more stop structures (Fig.1D, elements #176 and #165, Fig.1B there are multiple such structures); in contact with the corresponding conductive layers (Fig.1D, the stop structure is in contact with elements #146 and #246); and extending through the staircase region of the stack structure in a first direction toward the semiconductor layer (Fig.1D, stop structure extends vertically towards the semiconductor layer, element #110); and second dielectric layers (Fig.1, elements #242’), each between two of the first dielectric layers (Fig.1D, elements #242’ are between elements #232’), wherein each of the one or more stop structures is between one of the second dielectric layers and one of the conductive layers (Fig.1D, elements #176 are located between elements #242’ and #246, and element #165 is between bottom element #242’ and bottom element #146), and one or more dummy structures, each of the dummy structures is between two of the stop structures (Fig.29A, elements #128 inside regions #165).
Regarding claim 3, Shimomura teaches the 3D memory device of claim 1 as set forth in the anticipation rejection. Shimomura further teaches the 3D memory device of claim 1, wherein the one or more stop structures comprise one or more first stop structures (Fig.1B, horizontal walls of elements #176) and two or more second stop structures (Fig.1B, vertical walls of elements #176), wherein the one or more first stop structures extend in a second direction perpendicular to the first direction (Fig.1B, horizontal walls of elements #176 extend in the horizontal direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110) and the two or more second stop structures extend in a third direction perpendicular to the first direction and the second direction (Fig.1B, vertical sides of elements #176 extend in the vertical direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110 and perpendicular to the second direction), wherein one of the first stop structures connects two of the second stop structures (Fig.1B, the horizontal walls of element #176 connect the vertical walls of element #176).
Regarding claim 4, Shimomura teaches the 3D memory device of claim 1 as set forth in the anticipation rejection. Shimomura further teaches the 3D memory device of claim 1, further comprising: one or more first supporting structures in contact with the semiconductor layer and extending through the core region of the stack structure (Fig.5, elements #148 are in contact with semiconductor layer #110 and extend through the core region, element #100), wherein the one or more dummy structures are in contact with the semiconductor layer and extend through the staircase region of the stack structure (Fig.29C, elements #128 in region #200 extend through the staircase region and contact element #110).
Regarding claim 6, Shimomura teaches the 3D memory device of claim 1 as set forth in the anticipation rejection. Shimomura further teaches the 3D memory device of claim 1, comprising two or more dummy structures wherein the two or more dummy structures are arranged side-by-side along a second direction in which the stop structures extend, wherein the second direction is perpendicular to the first direction (Fig.19A, elements #128 inside region #165 are arranged sided by side in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110).
Regarding claim 9, Shimomura teaches the 3D memory device of claim 1 as set forth in the anticipation rejection. Shimomura further teaches The 3D memory device of claim 1, wherein the one or more stop structures comprise one or more first stop structures (Fig.1B, horizontal walls of elements #176) and two or more second stop structures (Fig.1B, vertical walls of elements #176 and element #165), wherein the one or more first stop structures extend in a second direction perpendicular to the first direction (Fig.1B, horizontal walls of elements #176 extend in the horizontal direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110), and the two or more second stop structures extend in a third direction perpendicular to the first direction and the second direction (Fig.1B, vertical walls of element #176 and element #165 extend in the vertical direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110, and perpendicular to the second direction), wherein one of the first stop structures connects two of the second stop structures, and wherein one of the second stop structures extends in the first direction and is in contact with one of the first dielectric layer (Fig.1B, the horizontal walls of elements #176 connect the two vertical walls of element #176 and are in contact with element, and Fig.1D are in contact with elements #132, #232, and #232’).
Regarding claim 10, Shimomura teaches the 3D memory device of claims 1 and 9 as set forth in the anticipation rejection. Shimomura further teaches the 3D memory device of claim 9, wherein one of the second stop structures has a rectangular cross-section (vertical walls of elements #176 have a rectangular cross section, paragraph [0071], rows 15-20).
Regarding claim 11, Shimomura teaches the 3D memory device of claims 1 and 9 as set forth in the anticipation rejection. Shimomura further the 3D memory device of claim 1, wherein the one or more stop structures comprise one or more first stop structures Fig.1B, horizontal walls of elements #176) and two or more second stop structures (Fig.1B, vertical walls of elements #176 and element #165), wherein the one or more first stop structures extend in a second direction perpendicular to the first direction (Fig.1B, horizontal walls of elements #176 extend in the horizontal direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110), and the two or more second stop structures extend in a third direction perpendicular to the first direction and the second direction (Fig.1B, vertical walls of element #176 and element #165 extend in the vertical direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110, and perpendicular to the second direction), wherein one of the first stop structures connects two of the second stop structures (Fig.1B, one horizontal wall of element #176 connect the two vertical walls of element #176), and wherein one of the second stop structures has a stepwise cross-section (Fig.1D, element #165 has a stepwise cross section).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shimomura, in view of Tao et al., (United States Patent Application Publication Number, US 2019/0341399 A1) hereinafter referenced as Tao.
Regarding claim 2, Shimomura teaches the 3D memory device of claim 1 as set forth in the anticipation rejection. Shimomura further teaches. the 3D memory device of claim 1, wherein a material of the second dielectric layers is different from that of the stop structures (second dielectric layers, element #242’, same as element #242 are made of silicon nitride, paragraph [0195], rows 11-12, and stop structure, element #176, is made of silicate glass, which is composed of silicon oxide paragraph [0174], rows 1-3).
Shimomura further teaches that the second dielectric layers (which are made of silicon nitride, paragraph [0195], rows 11-12) may be removed selectively with respect to the first dielectric layers (paragraph [0195], rows 1-5) and the stop structure and the first dielectric layers are made of same materials, silicon oxide (paragraph [0174], rows 1-3 and paragraph [0137], rows 9-15). Shimomura does not teach that a material of the second dielectric layers and that of the stop structures have an etching selectivity of equal or more than 5. Tao teaches a wet etch chemistry that can remove silicon nitride with an etch selectivity more than 500:1 in comparison to silicon oxide (paragraph [0079], rows 1-6). Therefore, the combination of Shimomura and Tao teaches a material of the second dielectric layers and that of the stop structures have an etching selectivity of equal or more than 5. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tao and disclose a material of the second dielectric layers and that of the stop structures have an etching selectivity of equal or more than 5. As disclosed by Tao, this allows etching the second dielectric layers without affecting the first dielectric layers, and replacing the etch regions with conductive layers (paragraph [0079], rows 10-12 and paragraph [0080], rows 1-3).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Shimomura, in view of Kubo (United States Patent Application Publication Number, US 2022/0102375 A1) hereinafter referenced as Kubo, and in view of Kitazawa (United States Patent Application Publication Number, US 2021/0159149 A1) hereinafter referenced as Kitazawa.
Regarding claim 5, Shimomura teaches the 3D memory device of claim 1 as set forth in the anticipation rejection. Shimomura does not teach the 3D memory device of claim 1, wherein a diameter of each of dummy structures is larger than a width of each of the stop structures, and the diameter of each of the dummy structures is ranged from 50 nm to 300 nm. Kubo teaches wherein a width of each of the stop structures can be 50 nm (Fig.20B, paragraph [0279], rows 1-3). The combination of Shimomura and Kubo does not teach the diameter of each of the second supporting structures is ranged from 50 nm to 300 nm. However, Shimomura teaches the width of the dummy structure is the same as the width of the support structures in the staircase region (Fig.29A, elements #128 inside and outside areas #165). Kitazawa teaches the diameter of each of the support structures in the staircase region is in the range from 50nm to 300nm (element #129, paragraph [0075], rows 1-4). Thus, the combination of Shimomura, Kubo and Kitazawa teaches wherein a diameter of each of the dummy structures is larger than a width of each of the stop structures, and the diameter of each of the second dummy structure is ranged from 50 nm to 300 nm. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kubo and Kitazawa and disclose wherein a diameter of each of the dummy structures is larger than a width of each of the stop structures. Making the dummy structures the same as the supporting structure in the staircase region saves processing steps and thus reduces cost and increases yield. Furthermore, the diameter of the supporting structures in the staircase region (and so the diameter of the dummy structures manufactured during the same process steps) is a result effective variable which is determined by that thickness and number of the alternating layers in the staircase region, where the diameter of the support structures increases with the number of layers and it has to be wide enough to provide the necessary mechanical support. Also, the claimed range for the diameter of the dummy structures overlaps or lies inside the range disclosed by Kitazawa and therefore a prima facie case of obviousness exists (MPEP 2144.05). The stop structure is not needed for mechanical stability, and therefore a width of the stop structure is independent of the number of alternating layers of the staircase region, and very thin layers (small width) can prevent etching of the dielectric layers surrounded by the stop structure using a highly selective wet etch.
Claims 12, 22, 23 and 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura, in view of Huo et al., (United States Patent Application Publication Number, US 2011/0101443 A1) hereinafter referenced as Huo.
Regarding claim 12, Shimomura teaches a system, comprising: a three-dimensional (3D) memory device configured to store data (Fig.1A, formed by elements #100 and #200), the 3D memory device comprising: a semiconductor layer (Fig.1D, element #110); a stack structure on the semiconductor layer (Fig.1D, formed by all the elements in the figure), wherein the stack structure comprises alternating conductive layers (Fig.1D, elements #146 and #246) and first dielectric layers (Fig.1D, elements #132, #232, and #232’) and has a core region (Fig.1D, elements #100) and a staircase region adjacent to the core region (Fig.1D, elements #200); one or more stop structures (Fig.1D, elements #176 and #165) in contact with the corresponding conductive layers (Fig.1D, the stop structure is in contact with elements #146 and #246) and extending through the staircase region of the stack structure in a first direction toward the semiconductor layer (Fig.1D, stop structure extends vertically towards the semiconductor layer, element #110); second dielectric layers (Fig.1, element #242’), each between two of the first dielectric layers (Fig.1D, elements #242’ are between elements #232’), wherein each of the one or more stop structures is between one of the second dielectric layers and one of the conductive layers (Fig.1D, elements #176 are located between elements #242’ and #246, and element #165 is between bottom element #242’ and bottom element #146), and one or more dummy structures, each of the dummy structures is between two of the stop structures (Fig.29A, elements #128 inside regions #165). Shimomura does not teach a memory controller coupled to the 3D memory device and configured to control the 3D memory device. Huo teaches a memory controller coupled to a 3D memory device and configured to control the 3D memory device (Fig.13, element#1110, paragraph [0130], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Huo and disclose a memory controller coupled to a 3D memory device and configured to control the 3D memory device. The memory controller is a necessary interface through each data writing and reading commands are transmitted to the memory system.
Regarding claim 22, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 12, wherein the one or more stop structures comprise one or more first stop structures (Fig.1B, horizontal walls of elements #176) and two or more second stop structures (Fig.1B, vertical walls of elements #176), wherein the one or more first stop structures extend in a second direction perpendicular to the first direction (Fig.1B, horizontal walls of elements #176 extend in the horizontal direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110) and the
Regarding claim 23, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 12, wherein the 3D memory device further comprises: one or more first supporting structures in contact with the semiconductor layer and extending through the core region of the stack structure (Fig.5, elements #148 are in contact with semiconductor layer #110 and extend through the core region, element #100), wherein the one or more dummy structures are in contact with the semiconductor layer and extend through the staircase region of the stack structure (Fig.29C, elements #128 located in region #165 extend through the staircase region and contact element #110).
Regarding claim 25, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 12, comprising two or more dummy structures wherein the two or more dummy structures are arranged side-by- side along a second direction in which the stop structures extend, wherein the second direction is perpendicular to the first direction (Fig.19A, elements #128 inside region #165 are arranged sided by side in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110).
Regarding claim 26, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 12, wherein the one or more stop structures comprise one or more first stop structures (Fig.1B, horizontal walls of elements #176) and two or more second stop structures (Fig.1B, vertical walls of elements #176 and element #165), wherein the one or more first stop structures extend in a second direction perpendicular to the first direction (Fig.1B, horizontal walls of elements #176 extend in the horizontal direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110), and the two or more second stop structures extend in a third direction perpendicular to the first direction and the second direction (Fig.1B, vertical walls of element #176 and element #165 extend in the vertical direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110, and perpendicular to the second direction), wherein one of the first stop structures connects two of the second stop structures, and wherein one of the second stop structures extends in the first direction and is in contact with one of the first dielectric layer (Fig.1B, the horizontal walls of elements #176 connect the two vertical walls of element #176 and are in contact with element, and Fig.1D are in contact with elements #132, #232, and #232’).
Regarding claim 27, the combination of Shimomura and Huo teaches the system of claims 12 and 26 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 16, wherein one of the second stop structures has a rectangular cross-section (vertical walls of elements #176 have a rectangular cross section, paragraph [0071], rows 15-20).
Regarding claim 28, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 12, wherein the one or more stop structures comprise one or more first stop structures (Fig.1B, horizontal walls of elements #176) and two or more second stop structures (Fig.1B, vertical walls of elements #176 and element #165), wherein the one or more first stop structures extend in a second direction perpendicular to the first direction (Fig.1B, horizontal walls of elements #176 extend in the horizontal direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110), and the two or more second stop structures extend in a third direction perpendicular to the first direction and the second direction (Fig.1B, vertical walls of element #176 and element #165 extend in the vertical direction, in a plane perpendicular to the first direction, where the first direction is perpendicular to the semiconductor element #110, and perpendicular to the second direction), wherein one of the first stop structures connects two of the second stop structures (Fig.1B, one horizontal wall of element #176 connect the two vertical walls of element #176), and wherein one of the second stop structures has a stepwise cross-section (Fig.1D, element #165 has a stepwise cross section).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Shimomura, in view of Huo and view of Tao.
Regarding claim 21, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. Shimomura further teaches the system of claim 12, wherein a material of the second dielectric layers is different from that of the stop structures (second dielectric layers, element #242’, same as element #242 are made of silicon nitride, paragraph [0195], rows 11-12, and stop structure, element #176, is made of silicate glass, which is composed of silicon oxide paragraph [0174], rows 1-3). Shimomura also teaches that the second dielectric layers (which are made of silicon nitride, paragraph [0195], rows 11-12) may be removed selectively with respect to the first dielectric layers (paragraph [0195], rows 1-5) and the stop structure and the first dielectric layers are made of same materials, silicon oxide (paragraph [0174], rows 1-3 and paragraph [0137], rows 9-15).
The combination of Shimomura and Huo does not teach that a material of the second dielectric layers and that of the stop structures have an etching selectivity of equal or more than 5. Tao teaches a wet etch chemistry that can remove silicon nitride with an etch selectivity more than 500:1 in comparison to silicon oxide (paragraph [0079], rows 1-6). Therefore, the combination of Shimomura, Huo and Tao teaches a material of the second dielectric layers and that of the stop structures have an etching selectivity of equal or more than 5. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tao and disclose a material of the second dielectric layers and that of the stop structures have an etching selectivity of equal or more than 5. As disclosed by Tao, this allows etching the second dielectric layers without affecting the first dielectric layers, and replacing the etch regions with conductive layers (paragraph [0079], rows 10-12 and paragraph [0080], rows 1-3).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Shimomura, in view of Huo, Kubo, and Kitazawa .
Regarding claim 24, the combination of Shimomura and Huo teaches the system of claim 12 as set forth in the obviousness rejection. The combination of Shimomura and Huo does not teach the system of claim 12, wherein a diameter of each of dummy structures is larger than a width of each of the stop structures, and the diameter of each of the dummy structures is ranged from 50 nm to 300 nm. Kubo teaches wherein a width of each of the stop structures can be 50 nm (Fig.20B, paragraph [0279], rows 1-3). The combination of Shimomura, Huo and Kubo does not teach the diameter of each of the second supporting structures is ranged from 50 nm to 300 nm. However, Shimomura teaches the width of the dummy structure is the same as the width of the support structures in the staircase region (Fig.29A, elements #128 inside and outside areas #165). Kitazawa teaches the diameter of each of the support structures in the staircase region is in the range from 50nm to 300nm (element #129, paragraph [0075], rows 1-4). Thus, the combination of Shimomura, Huo, Kubo and Kitazawa teaches wherein a diameter of each of the dummy structures is larger than a width of each of the stop structures, and the diameter of each of the second dummy structure is ranged from 50 nm to 300 nm. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kubo and Kitazawa and disclose wherein a diameter of each of the dummy structures is larger than a width of each of the stop structures. Making the dummy structures the same as the supporting structure in the staircase region saves processing steps and thus reduces cost and increases yield. Furthermore, the diameter of the supporting structures in the staircase region (and so the diameter of the dummy structures manufactured during the same process steps) is a result effective variable which is determined by that thickness and number of the alternating layers in the staircase region, where the diameter of the support structures increases with the number of layers and it has to be wide enough to provide the necessary mechanical support. Also, the claimed range for the diameter of the dummy structures overlaps or lies inside the range disclosed by Kitazawa and therefore a prima facie case of obviousness exists (MPEP 2144.05). The stop structure is not needed for mechanical stability, and therefore a width of the stop structure is independent of the number of alternating layers of the staircase region, and very thin layers (small width) can prevent etching of the dielectric layers surrounded by the stop structure using a highly selective wet etch.
Response to Arguments
Applicant’s arguments filed on 12/08/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899