DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant asserts in the reply that “Yang does not qualify as prior art under the America Invents Act due to common ownership and therefore cannot be properly applied in a § 102 or § 103 rejection” and “Yang should be removed from the prior art because of the common ownership exception under 35 U.S.C. 102(b)(2)(C).”
MPEP 717.02(a)(I) sets forth that “[i]n order to invoke common ownership to except a disclosure as prior art, the applicant (or the patent owner) must provide a statement that the disclosure of the subject matter on which the rejection is based and the claimed invention were owned by the same person or subject to an obligation of assignment to the same person not later than the effective filing date of the claimed invention. The statement should either be on or begin on a separate sheet and must not be directed to other matters (37 CFR 1.4(c)). The statement must be signed in accordance with 37 CFR 1.33(b).”
The applicant here has not fulfilled the requirements for such a statement (e.g., beginning on separate sheet). Thus the relevant exception has not been properly invoked.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, and 20-33 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, US 2023/0354599, in view of Lee, US 2011/0092060.
Claim 1: Yang discloses
a semiconductor layer (502+532);
and an array of memory cells disposed on the semiconductor layer, wherein each of the memory cells comprises:
a semiconductor body (510) extending in a first direction, wherein a first end of the semiconductor body is in contact with the semiconductor layer (FIG. 1);
a word line gate (WL1, WL2) extending in a second direction perpendicular to the first direction;
a plurality of plate line gates (PL1, PL2) extending in the second direction;
and a dielectric layer (512) disposed between the semiconductor body and the word line gate and the plurality of plate line gates (FIGS 5, 12K):
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Yang discloses a peripheral circuit ([0102]). It was known in the art to have memory cells aside (to the side of) the peripheral circuit. See e.g. Lee, FIG. 28 which discloses a peripheral circuit formed to the side of the memory area, and on the same substrate 200.
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It would have been obvious to have done so to form a complete device on a semiconductor circuit in a common and known way.
Claim 1 also recites a stairstep connection structure, which is disclosed by Yang. See Yang FIG. 12K, which shows contact structures extending in the first (vertical) direction, wherein the plurality of plate line gates recede from bottom to top to form a staircase structure; and each contact structure of the plurality of contact structures is in contact with one of the plurality of plate line gates:
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Claim 2: the plurality of plate line gates comprise a plurality of conductive lines (plate lines PL) extending in the second direction parallel to the word line gate (Yang FIG. 5).
Claim 3: the semiconductor body (silicon) and the semiconductor layer comprise a same semiconductor material (silicon, e.g. silicon-on-insulator) ([0040]-[0043]).
Claim 4: Sukui discloses a bit line (BL) extending in a third direction perpendicular to the first direction and the second direction, wherein a second end of the semiconductor body is in contact with the bit line (FIG. 1).
Claim 28: the first end of the semiconductor body (510) is in contact with a source line (source line contact 523, FIG. 5).
Claim 29: the first end (522) and the second end (532) of the semiconductor body comprise N+ semiconductor layers (FIG. 5). The “ends” of the semiconductor body can be considered ends that are internal or external to the body.
Claim 5: Yang discloses a contact (522, FIG. 5) disposed between the bit line and the second end of the semiconductor body.
Claim 6: the semiconductor layer comprises a memory area and a peripheral area, the array of memory cells is disposed in the memory area, and the peripheral circuit is disposed in the peripheral area (Lee FIG. 28).
Claim 26: Yang discloses a second contact structure (530) extending in the first direction in contact with the semiconductor layer.
Claim 27: the word line gate and the plurality of plate line gates are isolated by a second dielectric layer (portion of 512 between them).
Claim 20: Yang discloses
a semiconductor layer (502+532);
and an array of memory cells disposed on the semiconductor layer, wherein each of the memory cells comprises:
a semiconductor body (510) extending in a first direction, wherein a first end of the semiconductor body is in contact with the semiconductor layer (FIG. 5);
a word line gate (WL0/WL1) extending in a second direction perpendicular to the first direction;
a plurality of plate line gates (PL1, PL2) extending in the second direction;
and a dielectric layer (512) disposed between the semiconductor body and the word line gate and the plurality of plate line gates;
and a memory controller ([0102]) coupled to the memory device and configured to control operations of the array of memory cells.
Yang discloses a peripheral circuit ([0102]), stating that the invention. It was known in the art to have memory cells aside (to the side of) the peripheral circuit. See e.g. Lee, which discloses a peripheral circuit formed to the side of the memory area, and on the same substrate 200. It would have been obvious to have done so to form a complete device on a semiconductor circuit in a common way.
Claim 20 also recites a stairstep connection structure, which is disclosed by Yang. See Yang FIG. 12K, which shows contact structures extending in the first (vertical) direction, wherein the plurality of plate line gates recede from bottom to top to form a staircase structure; and each contact structure of the plurality of contact structures is in contact with one of the plurality of plate line gates.
Claim 21: the plurality of plate line gates comprise a plurality of conductive lines extending in the second direction parallel to the word line gate. Yang FIG. 5.
Claim 22: Yang discloses a silicon semiconductor body (“pillar 510 can include a semiconductor material, for example, Si” Yang [0142]). Yang discloses that the semiconductor layer 502 is a silicon ([0141]).
Claim 23: there is a bit line extending in a third direction perpendicular to the first direction and the second direction, wherein a second end of the semiconductor body is in contact with the bit line. Yang FIG. 5, 12K.
Claim 32: the first end of the semiconductor body (510) is in contact with a source line (source line contact 532).
Claim 22: the first end (522) and the second end (532) of the semiconductor body comprise N+ semiconductor layers. The “ends” of the semiconductor body can be considered ends that are internal or external to the body.
Claim 24: there is a contact (Yang 522, FIG. 5) disposed between the bit line and the second end of the semiconductor body.
Claim 25: the semiconductor layer comprises a memory area and a peripheral area, the array of memory cells is disposed in the memory area, and the peripheral circuit is disposed in the peripheral area (Lee FIG. 28).
Claim 30: the memory device further comprising: a second contact structure (530) extending in the first direction in contact with the semiconductor layer.
Claim 31: the word line gate and the plurality of plate line gates are isolated by a second dielectric layer (the portion of 512 between them).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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