DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-17 are pending in this application. Claims 4-16 were previously withdrawn as set forth in the office action mailed 10/7/2025.
Drawings
Prior objection to drawings is withdrawn in view of replacement drawings.
Specification
The disclosure is objected to because of the following informalities:
In the amended specification filed on 1/7/2026, it appears that the applicant has erroneously indicated the wrong paragraphs to be amended. The examiner believes that the paragraphs to be amended are [0113] and [0114], and not [0134] and [0135], as the applicant has indicated.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rabkin et al. (US 2020/0203362 A1, newly cited).
Re Claim 1, Rabkin teaches a semiconductor device (Figs. 13A and 13B), comprising:
a stack structure (32+46, Fig. 13A, para [0127]) including alternately stacked dielectric layers (32, para [0042]) and conductive layers (46, para [0127]), the conductive layers including a top select gate layer (top gate electrode in the stack may function as the select gate electrode, para [0047]); and
channel holes (58, Fig. 13A, para [0097]) penetrating through the stack structure (32+46),
wherein the top select gate layer (top 46 layer, Fig. 13A) is provided with a first top select gate isolation structure (72, Figs. 13A and 13B, para [0055]) and a second top select gate isolation structure (marked “2nd isolation structure” in annotated Fig. 13B below), the channel holes (58) being located (see Figs. 13A and 13B) between the first top select gate isolation structure (72) and the second top select gate isolation structure (“2nd isolation structure”), and
the second top select gate isolation structure (“2nd isolation structure”) includes an insulation portion (74, Fig. 13B, para [0120]), the insulation portion being divided into a plurality of second top select gate isolation substructures (marked “74-1” and “74-2”, in annotated Fig. 13B below), with spaces between adjacent ones of the plurality of second top select gate isolation substructures filled with a conductive substance to form a plurality of inter-substructure conductive portions (76A+76B, Fig. 13B, para [0123]).
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Re Claim 2, Rabkin teaches the semiconductor device of claim 1, wherein the insulation portion (74) of the second top select gate isolation structure (“2nd isolation structure”) is divided in a first direction (vertical-axis in Fig. 13B) into a plurality of strip-shaped second top select gate isolation substructures (“74-1” and “74-2”, see annotated Fig. 13B above) extending in a second direction (horizontal-axis in Fig. 13B) perpendicular to the first direction (vertical-axis in Fig. 13B).
Re Claim 3, Rabkin teaches the semiconductor device of claim 2, wherein the plurality of second top select gate isolation substructures (“74-1” and “74-2”, see annotated Fig. 13B above) are distributed side by side in the first direction (vertical-axis in Fig. 13B), and the plurality of second top select gate isolation substructures have the same dimension in the first direction (width of “74-1” and “74-2” along the vertical-axis are same).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US 2020/0203362 A1, newly cited), and further in view of Lee et al. (US 2019/0363100 A1, of record).
Re Claim 17, Rabkin teaches a memory system, comprising a memory, the memory including a semiconductor device (Figs. 13A and 13B),
wherein the semiconductor device includes a stack structure (32+46, Fig. 13A, para [0127]) and channel holes (58, Fig. 13A, para [0097]),
the stack structure (32+46) includes alternately stacked dielectric layers (32, para [0042]) and conductive layers (46, para [0127]), the conductive layers including a top select gate layer (top gate electrode in the stack may function as the select gate electrode, para [0047]),
the channel holes (58, Fig. 13A, para [0097]) penetrating through the stack structure (32+46),
the top select gate layer (top 46 layer, Fig. 13A) is provided with a first top select gate isolation structure (72, Figs. 13A and 13B, para [0055]) and a second top select gate isolation structure (marked “2nd isolation structure” in annotated Fig. 13B above), the channel holes (58) being located (see Figs. 13A and 13B) between the first top select gate isolation structure (72) and the second top select gate isolation structure (“2nd isolation structure”), and
the second top select gate isolation structure (“2nd isolation structure”) includes an insulation portion (74, Fig. 13B, para [0120]), the insulation portion being divided into a plurality of second top select gate isolation substructures (marked “74-1” and “74-2”, in annotated Fig. 13B above), with spaces between adjacent ones of the plurality of second top select gate isolation substructures filled with a conductive substance to form a plurality of inter-substructure conductive portions (76A+76B, Fig. 13B, para [0123]).
Rabkin is silent about a controller being coupled with the memory.
However, related semiconductor art, Lee, discloses a controller device (1100, Fig. 4, para [0079]) which is configured to control reading, writing, erasing, and background operations of the memory device (para [0081]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to incorporate a controller into the memory device of Rabkin as disclosed by Lee, because the controller is configured to control reading, writing, erasing, and background operations of the memory device (para [0081], Lee).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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