DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikegami et al., US Pub. No. 2014/0110723.
Re claim 1, Ikegami et al. disclose a silicon carbide semiconductor device, comprising: a silicon carbide semiconductor substrate 101/buffer of a first conductivity type (fig. 1a, i.e., n-type), the silicon carbide semiconductor substrate having a main surface (fig. 1a); a first semiconductor layer 102/102d of the first conductivity type (fig. 1a, i.e., n-type), provided on the main surface of the silicon carbide semiconductor substrate(fig. 1a), the first semiconductor layer having a first surface and a second surface opposite to each other (fig. 1a), the second surface of the first semiconductor layer facing the silicon carbide semiconductor substrate (fig. 1a), the first semiconductor layer having an impurity concentration that is lower than an impurity concentration of the silicon carbide semiconductor substrate (fig. 1a and/or paragraph 147 etc.); a first semiconductor region 103b of a second conductivity type (fig. 1a, i.e., p-type), provided at the first surface of the first semiconductor layer, the first semiconductor region having a first surface and a second surface opposite to each other (fig. 1a), the second surface of the first semiconductor region facing the silicon carbide semiconductor substrate (fig. 1a); a second semiconductor region 104 of the first conductivity type (fig. 1a, i.e., n-type), selectively provided in the first semiconductor region (fig. 1a), at the first surface of the first semiconductor region (fig. 1a); a trench 120 that penetrates through the first semiconductor region 103b and the second semiconductor region 104, and reaches the first semiconductor layer 102 (fig. 1a); a gate insulating film 107 provided in the trench (fig. 1a), along a bottom and a sidewall of the trench (fig. 1a); a gate electrode 108 provided in the trench, on the gate insulating film (fig. 1a); a third semiconductor region 106 of the first conductivity type (fig. 1a, i.e., n-type), provided between the first semiconductor region 103b and the gate insulating film 107 provided along the sidewall of the trench 120 (fig. 1a); and a fourth semiconductor region 103a (e.g., fig. 1a; in this case, only a portion of 103a is considered as the fourth semiconductor region i.e., the bottom half portion of the 103a) of the second conductivity type (fig. 1a, i.e., p-type), provided between the first semiconductor region 103b and the third semiconductor region 106 (fig. 1a), the fourth semiconductor region 103a (e.g., the bottom half portion of the 103a) having an impurity concentration that is higher than an impurity concentration of the first semiconductor region 103b, the fourth semiconductor region (the bottom half portion of the 103a) having a thickness that is thinner than a thickness of the first semiconductor region 103b (e.g., fig. 1a), and a part of a bottom of the fourth semiconductor region (the bottom half portion of the 103a) being in contact with the first semiconductor layer 102d (fig. 1a, paragraph 108, 141 etc.), see figs. 1a-48 and pages 1-28 for more details.
Re claim 2. The silicon carbide semiconductor device according to claim 1, wherein the third semiconductor region 106 has a width, in a direction orthogonal to the sidewall of the trench, greater than 0nm but not more than 50nm (i.e., 30nm, paragraph 126), the fourth semiconductor region 103a has a width in the direction orthogonal to the sidewall of the trench, greater than 10nm but not more than 200nm (i.e., 50nm, paragraph 128), and the first semiconductor region 103b is apart from the gate insulating film 107 of the sidewall of the trench 120, with a distance of at least 100nm therebetween in the direction orthogonal to the sidewall of the trench (i.e., 100nm, paragraph 160).
Re claim 3. The silicon carbide semiconductor device according to claim 2, wherein the impurity concentration of the fourth semiconductor region 103a (fig. 1 and paragraph 127) is at least 1 x1018/cm3, and the impurity concentration of the first semiconductor region 103b (i.e., fig. 1 and paragraph 138, 1x1017/cm3) is at least 5x1 016/cm3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ikegami et al., US Pub. No. 2014/0110723.
Ikegami et al. disclosed above, although the exact recitation “the third semiconductor region is of a same impurity concentration as that of the first semiconductor layer” of instant claim 5 is not explicitly stated by Ikegami et al. in the related text.
However, the concentration of claim 5 is considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller, the selection of reaction parameters such as temperature and concentration would have been obvious:
“Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed Acritical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”
In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Therefore, one of ordinary skill in the requisite art before the invention was made would have used any concentration range suitable to the device of Ikegami et al. in order to optimize the performance of the device. Furthermore, the specification contains no disclosure of either the critical nature of the claimed arrangement (i.e. - the third semiconductor region is of a same impurity concentration as that of the first semiconductor layer) or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the Applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).
Response to Arguments
Applicant's arguments filed 10/7/2025 have been fully considered but they are not persuasive for reasons herein above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACK S CHEN/ Primary Examiner, Art Unit 2893