DETAILED ACTION
This Action is responsive to the communication filed on 12/29/2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 7 recites the limitation: “the liner material comprises the said or a second transition metal and the said or a second chalcogen” (emphasis added) in lines 1-2. It is unclear how the clear is to be interpreted given the claimed language.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 11, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0294998), in view of Dewey (US 2020/0105751).
Regarding claim 1, Lilak (see, e.g., FIG. 1A) discloses a transistor structure, comprising:
a source terminal 124B (left) and a drain terminal 124B (right) within an integrated circuit (IC) die e.g., integrated circuit structure of FIG. 1A, wherein the source and drain terminals 124B (left), 124B (right) each comprise a liner material e.g., carbon-containing SiGe liner and a bulk material e.g., SiGe body (Para 0025);
a nanoribbon 116B between and coupled to the source and drain terminals 124B (left), 124B (right), and wherein at least a portion of the liner material e.g., carbon-containing SiGe liner is between the nanoribbon 116B and the bulk material e.g., SiGe body (Para 0013, Para 0015, Para 0025);
a gate electrode material 120B coupled to the nanoribbon 116B (Para 0013); and
a gate insulator layer 122B between the nanoribbon 116B and the gate electrode material 120B (Para 0013, Para 0025).
Although Lilak shows substantial features of the claimed invention, Lilak fails to expressly teach the nanoribbon comprises a transition metal and a chalcogen.
Dewey (see, e.g., FIG. 2a) teaches that the nanoribbon 202 comprises a transition metal e.g., molybdenum (Mo) and a chalcogen e.g., sulfur (S) for the purpose of providing high mobility TFT nanoribbon structures thereby providing improved performance such as electrostatic gate control and improved immunity to short channel effects (Para 0014, Para 0022, Para 0027).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of nanoribbons of Lilak to the be nanoribbon comprising a transition metal and a chalcogen as described by Dewey for the purpose of providing high mobility TFT nanoribbon structures thereby providing improved performance such as electrostatic gate control and improved immunity to short channel effects (Para 0014, Para 0022, Para 0027).
Regarding claim 2, Lilak (see, e.g., FIG. 1A) teaches the transistor structure of claim 1, wherein the liner material e.g., carbon-containing SiGe liner directly contacts an end of the nanoribbon 116B.
Regarding claim 4, Lilak (see, e.g., FIG. 1A) teaches the transistor structure of claim 1, wherein the source and drain terminals 124B (left), 124B (right) are in an interconnect layer 108 of the IC die e.g., integrated circuit structure of FIG. 1A, the interconnect layer 108 above a device layer 104 (Para 0012, Para 0013, Para 0029).
Regarding claim 5, Lilak (see, e.g., FIG. 1A) teaches the transistor structure of claim 1, wherein the liner material e.g., carbon-containing SiGe liner comprises at least one of antimony, gold, silver, nickel, titanium, ruthenium, tin, bismuth, aluminum, germanium, tantalum, palladium, platinum, iridium, tungsten, rhodium, or molybdenum (Para 0025).
Regarding claim 11, the combination of Lilak (see, e.g., FIG. 1A) / Dewey (see, e.g., FIG. 2a) teaches transistor structure of claim 1, wherein the nanoribbon 116B (as taught by Lilak) is one of a plurality of nanoribbons 116B (as taught by Lilak) between and directly contacting the source and drain terminals 124B (left), 124B (right) (as taught by Lilak), individual ones of the nanoribbons 116B (as taught by Lilak) comprise a channel region comprising a transition metal e.g., molybdenum (Mo) (as taught by Dewey) and a chalcogen e.g., sulfur (S) (as taught by Dewey), and the liner material e.g., carbon-containing SiGe liner directly contacts an end of each of the plurality of nanoribbons 116B (as taught by Lilak).
Regarding claim 13, Lilak (see, e.g., FIG. 1A, FIG. 10) discloses an integrated circuit (IC) device, comprising:
an IC die e.g., IC structure of FIG. 1A comprising a transistor, the transistor comprising:
a source terminal 124B (left) and a drain terminal 124B (right) within the IC die e.g., IC structure of FIG. 1A, wherein the source and drain terminals 124B (left), 124B (right) comprise a liner material e.g., carbon-containing SiGe liner and a bulk material SiGe body (Para 0025);
a plurality of nanoribbons 116B between and coupled to the source and drain terminals 124B (left), 124B (right), and wherein at least a portion of the liner material e.g., carbon-containing SiGe liner is between individual ones of the nanoribbons 116B and the bulk material SiGe body (Para 0013, Para 0015, Para 0025);
a gate electrode material 120B between and coupled to individual ones of the nanoribbons 116B (Para 0013); and
a gate insulator layer 122B between individual ones of the nanoribbons 116B and the gate electrode material 120B (Para 0013, Para 0015); and
a power supply e.g., battery (see FIG. 10) coupled to the IC die e.g., IC structure of FIG. 1A within 1006 (see FIG. 10) (Para 0063, Para 0066).
Although Lilak shows substantial features of the claimed invention, Lilak fails to expressly teach the individual ones of the nanoribbon comprise a transition metal and a chalcogen.
Dewey (see, e.g., FIG. 2a) teaches that the individual ones of the nanoribbon 202 comprises a transition metal e.g., molybdenum (Mo) and a chalcogen e.g., sulfur (S) for the purpose of providing high mobility TFT nanoribbon structures thereby providing improved performance such as electrostatic gate control and improved immunity to short channel effects (Para 0014, Para 0022, Para 0027).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of nanoribbons of Lilak to the be nanoribbons comprising a transition metal and a chalcogen as described by Dewey for the purpose of providing high mobility TFT nanoribbon structures thereby providing improved performance such as electrostatic gate control and improved immunity to short channel effects (Para 0014, Para 0022, Para 0027).
Regarding claim 14, Lilak (see, e.g., FIG. 1A, FIG. 10) teaches the IC device of claim 13, wherein the liner material e.g., carbon-containing SiGe liner directly contacts a plurality of ends of corresponding ones of the nanoribbons 116B.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0294998), in view of Dewey (US 2020/0105751), and further in view of Kim (US 2023/0081646).
Regarding claim 6, although Lilak/Dewey shows substantial features of the claimed invention, Lilak/Dewey fails to expressly teach transistor structure of claim 1, wherein the liner material comprises graphene.
Kim (see, e.g., FIG. 2) teaches that the liner material GB1, GB2 comprises graphene for the purpose of providing a material with high electrical mobility and excellent thermal properties (Para 0049, Para 0053).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of liner of Lilak/Dewey to be graphene as described by Kim for the purpose of providing a material with high electrical mobility and excellent thermal properties (Para 0049, Para 0053).
Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2024/0079465), in view of Dewey (US 2020/0105751), in view of Van Dal (US 2022/0393033), in view of Wu (US 2022/0190125).
Regarding claim 16, Cheng (see, e.g., FIG. 3A – FIG. 15B) discloses a method, comprising:
receiving a workpiece 200 comprising a substrate 202 (Para 0017);
forming a stack 207 of interleaved channel 208 and sacrificial layers 206 over the substrate 202 (Para 0018);
depositing a dielectric e.g., dielectric layer or sacrificial material (Para 0024);
opening voids e.g., by etching dielectric and recessing 206 in the dielectric e.g., dielectric layer or sacrificial material e.g., to form 218 (Para 0024);
forming a gate dielectric gate dielectric layer in gate stack 228 in a void e.g., void formed by recessing 206 between channel 208 (Para 0031); and
filling a metal gate electrode in gate stack 228 over the liner material or the gate dielectric gate dielectric layer in gate stack 228 (Para 0031).
Although Cheng shows substantial features of the claimed invention, Cheng fails to expressly teach the nanoribbon; and conformally depositing a liner material coupled to the nanoribbons.
Dewey (see, e.g., FIG. 2a) teaches the nanoribbons 202 for the purpose of providing high mobility TFT nanoribbon structures thereby providing improved performance such as electrostatic gate control and improved immunity to short channel effects (Para 0014, Para 0022, Para 0027).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel layers of Cheng to be nanoribbons as described by Dewey for the purpose of providing high mobility TFT nanoribbon structures thereby providing improved performance such as electrostatic gate control and improved immunity to short channel effects (Para 0014, Para 0022, Para 0027).
Van Dal (see, e.g., FIG. 2F) teaches conformally depositing a liner 124 (Para 0047-Para 0048, Para 0050). Wu, on the other hand, teaches that liners are key components to tuning the contact resistance of devices (Para 0043).
The combination of Cheng (see, e.g., FIG. 3A – FIG. 15B) / Dewey (see, e.g., FIG. 2a) / Van Dal (see, e.g., FIG. 2F) teaches conformally depositing a liner material 124 (as taught by Van Dal) coupled to the nanoribbons 208 (as taught by Cheng, modified by Dewey).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the liner as described by Van Dal/Wu to the device of Cheng/Dewey for the purpose of tuning the contact resistance of devices (Wu: Para 0043).
Regarding claim 17, the combination of Cheng (see, e.g., FIG. 3A – FIG. 15B) / Lilak teaches the method of claim 16, wherein conformally depositing the liner material e.g., carbon-containing SiGe liner (as taught by Lilak) directly contacts the liner material e.g., carbon-containing SiGe liner (as taught by Lilak) to a plurality of ends of corresponding ones of the nanoribbons 208 (as taught by Cheng, modified by Dewey).
Regarding claim 19, Van Dal (see, e.g., FIG. 2F) teaches method of claim 16, wherein conformally depositing the liner material 124 comprises a chemical vapor deposition or an atomic layer deposition (Para 0050).
Regarding claim 20, although Cheng shows substantial features of the claimed invention, Cheng fails to expressly teach that the substrate is over a device layer.
Dewey (see, e.g., FIG. 2a) teaches that the substrate 207 is over a device layer 209 for the purpose of forming top and bottom gate-all-around transistor device (Para 0017, Para 0027, Para 0028).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the device layer as described by Dewey to the device of Cheng for the purpose of forming a top and bottom gate-all-around transistor device (Para 0017).
Allowable Subject Matter
Claims 3, 8-10, 12, 15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817