DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-15, in the reply filed on February 3, 2026 is acknowledged.
Accordingly, claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 3, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 29, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 9, and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al (US Pub 2024/0107903).
In re claim 1, Lin et al discloses a transistor structure, comprising: a source terminal (i.e. 145) and a drain terminal (i.e. 145); a nanoribbon between and coupled to the source terminal and the drain terminal, wherein the nanoribbon comprises a channel layer (i.e. 120b), a first crystalline layer (i.e. 120a), and a second crystalline layer (i.e. 131/130) (i.e. see at least paragraph 0021 disclosing the use of crystalline material for at least layers 120, 130), wherein the channel layer is between the first crystalline layer and the second crystalline layer (i.e. see at least Figure 8), the channel layer comprising a metal and a chalcogen (i.e. see at least paragraph 0043); a gate electrode material (i.e. 154) adjacent the nanoribbon; and a gate insulator layer (i.e. 152) between the nanoribbon and the gate electrode material (i.e. see at least Figure 8).
In re claim 2, Lin et al discloses wherein the channel layer comprises a crystalline material (i.e. see at least paragraph 0021).
In re claim 5, Lin et al discloses wherein the first and second crystalline layers have substantially the same composition and crystalline structure (i.e. see at least paragraphs 0021, 0043).
In re claim 9, Lin et al discloses wherein the metal is at least tungsten or molybdenum and the chalcogen is at least sulfur (i.e. see at least paragraphs 0024, 0026, 0028).
In re claim 10, Lin et al discloses an integrated circuit (IC) device (i.e. see at least Figure 8), comprising: an IC die comprising a transistor (i.e. paragraph 0002 discloses integrated circuit (IC) technology and thus, it would have been implicit/inherent from Lin et al that an IC die would be used in their invention), the transistor comprising: a source terminal (i.e. 145) and a drain terminal (i.e. 145); a plurality of nanoribbons between and coupled to the source terminal and the drain terminal, wherein individual ones of the nanoribbons comprise a channel layer (i.e. 120b) between a first crystalline layer (i.e. 120a) and a second crystalline layer (i.e. 131/130) (i.e. see at least paragraph 0021 disclosing the use of crystalline material for at least layers 120, 130), the channel layer comprising a metal and a chalcogen (i.e. see at least paragraph 0043); a gate electrode (i.e. 154) material between and coupled to individual ones of the nanoribbons (i.e. at least electrically coupled); and a gate insulator layer (i.e. 152) between individual ones of the nanoribbons and the gate electrode material; and a power supply coupled to the IC die (i.e. it would have been inherent/implicit from Lin et al that there would be a power supply as it is well known in the art that a power supply is needed in order for the device to function).
Allowable Subject Matter
Claims 3, 4, 6-8, and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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