DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 5/13/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al. (US 2021/0074600) (“Jeng”).
With regard to claim 1, fig. 1F of Jeng discloses an apparatus comprising: a glass substrate 110 (“glass substrate”, par [0028]); a plurality of through vias 111 extending through a thickness of the glass substrate 110; a logic IC die 128 on a first side 11B of the glass substrate 110 and comprising first metallization features 113 facing the glass substrate 110, wherein first ones (113 under 128 not above 120) of the first metallization features 113 are coupled to first ones (111 under 128 and not above 120) of the through vias 111; and a memory (“memory”, par [0042]) IC die 120 in a stack with the logic (“logic circuitry”, par [0033]) IC die 128, the memory (“memory”, par [0042]) IC die 120 comprising second metallization features 122 facing, and coupled to, second ones (113 above 120) of the first metallization features 113.
With regard to claim 2, fig. 1F of Jeng discloses that the thickness of the glass substrate 110 is between the logic (“logic circuitry”, par [0033]) IC die 128 and the memory (“memory”, par [0042]) IC die 120; and the second ones (113 above 120) of the first metallization features 113 are coupled to a first end (top of 111 above 120) of second ones (111 above 120) of the through vias 111.
With regard to claim 3, fig. 1F of Jeng discloses that the first ones (113 under 128 and not above 120) of the first metallization features 113 are directly bonded (“direct metal-to-metal”, par [0034]) to the first ones of the through vias 111, and the second ones 123 of the first metallization features 130 are directly bonded (“direct metal-to-metal”, par [0043]) to the second ones (111 above 120) of the through vias 111.
With regard to claim 4, fig. 1F of Jeng discloses that the second metallization features 123 are directly bonded to a second end (bottom of 111 above 120) of the second ones (111 above 120) of the through vias 111.
With regard to claim 5, fig. 1F of Jeng discloses that the second metallization features 123 are coupled through solder (“solder”, par [0043]) features 123B to a second end (bottom of 111 above 120) of the second ones (111 above 120) of the through vias 111.
With regard to claim 6, fig. 1F of Jeng discloses that the solder features (“solder”, par [0043]) are first solder features 123; and the IC device logic (“logic circuitry”, par [0033]) IC die 128 further comprises second solder features 116 laterally adjacent to the memory (“memory”, par [0042]) IC die 120 and coupled to a second end (bottom of 111 under 128 not above 120) of the first ones (111 under 128 not above 120) of the through vias 111, the second solder features 116 having a lower reflow temperature (“elevated temperature”, par [0075]) than the first solder features 123B.
With regard to claim 7, fig. 1F of Jeng discloses solder features 113 (“solder bonding”, par [0043]) couple the first (130 under 128 not over 120) and second ones (130 over 120) of the first metallization features 113 to the first (111 under 18 not over 120) and second ones (111 over 120) of the through vias 111, the second solder features 116 having a lower reflow temperature (“elevated temperature”, par [0075]) than the first solder features 113.
With regard to claim 8, fig. 1F of Jeng discloses that the solder features are first solder (“solder bonding”, par [0043]) features 123; and the second metallization features 123 are coupled through second solder (“solder bonding”, par [0043]) features 123 to the second end (bottom of 111 above 120) of the second ones (111 above 120) of the through vias 111.
With regard to claim 9, fig. 1F of Jeng disclose logic IC die further comprises package-level solder interconnect 116 features laterally adjacent to the memory IC die 120 and coupled to the second end (bottom of 111 under 128 not above 120) of the first ones (111 under 128 not above 120) of the through vias 111, the package-level solder interconnect features 116 having a lower reflow temperature (“elevated temperature”, par [0075]) than the first solder features 113.
With regard to claim 10, fig. 1F of Jeng discloses logic IC die further comprises package-level solder interconnect 116 features laterally adjacent to the memory IC die 120 and coupled to a second end (bottom of 111 under 128 not above 120) of the first ones (111 under 128 not above 120) of the through vias 111.
With regard to claim 11, fig. 2 of Jeng discloses logic IC die (“logic circuitry”, par [0033]) further comprises: a package dielectric material 104 laterally adjacent to the memory (“memory”, par [0042]) IC die 120; and a routing structure 106 within the package dielectric material 104, the routing structure 104 comprising via metallization features in direct contact (“same or similar to those of the conductive structures 113”, par [0046]; (“direct metal-to-metal (such as a copper-to-copper) bonding”, par [0043]) with a second end (bottom of 111) of the first ones (111 under 128 not above 120) of the through vias 111, the routing structure 106 terminating at first-level interconnect interfaces (top of 106).
With regard to claim 12, fig. 1F of Jeng discloses at least one of the logic IC die or memory IC die 120 is embedded within the glass substrate 110 and at least a portion of a sidewall of the logic IC die or memory IC die 120 is laterally adjacent to the through vias 111 with a portion of the glass substrate 110 therebetween. With regard to claim 13, fig. 1F of Jeng discloses that the first ones (113 under 128 not above 120) of the first metallization features 113 are directly bonded to the first ones (111 under 128 not above 120) of the through vias 111, and the second ones (113 above 120) of the first metallization features 113 are directly bonded (“direct metal-to-metal (such as a copper-to-copper) bonding”, par [0043]) to the second metallization features 123.
With regard to claim 14, fig. 2 of Jeng discloses a system comprising: a multi-chip integrated circuit (IC) device comprising: a glass substrate 110 (“glass substrate”, par [0028]); a plurality of through vias 111 extending through a thickness of the glass substrate 110; a logic (“logic circuitry”, par [0033]) IC die 128 on a first side of the glass substrate 110 and comprising first metallization features 113 facing the glass substrate 110, wherein first ones of the first metallization features 113 are coupled to first ones of the through vias 111; and a memory (“memory”, par [0042]) IC die 120 in a stack with the logic IC die 128, the memory IC die 120 comprising second metallization features 123 facing, and coupled to, second ones (113 above 120) of the first metallization features 113 through second ones (111 above 120) of the through vias 111; a package dielectric material 104 adjacent to a sidewall of the memory IC die 120; a routing structure 106 embedded within the package dielectric material 104, the routing structure 106 comprising metallization features in contact with the first ones of the through vias 111 and terminating at first-level interconnect interfaces (top of 106); and a host component (“external device”, par [0051]) interconnected to the routing structure 106 through first-level interconnects 136 coupled to the first-level interconnect interfaces (top of 106).
With regard to claim 15, fig. 2 of Jeng discloses that the first-level interconnect features 136 comprise solder (“solder element to form the conductive bumps 136”, par [0052]).
With regard to claim 16, fig. 2 of Jeng discloses a power supply coupled through the host component (“external device”, par [0051]) to provide power to at least the logic IC die 128 through the first ones of the through vias 111.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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